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| author | Kyungwoo Lee <kyulee@microsoft.com> | 2016-03-11 23:51:46 -0800 |
|---|---|---|
| committer | Kyungwoo Lee <kyulee@microsoft.com> | 2016-03-15 16:36:55 -0700 |
| commit | 2300f42bdd35f7b971d6fbeb54d2678ea429ef34 (patch) | |
| tree | 1a22980e591deafd9557b650fb3131a79b5a55c9 /src/jit/emitfmtsarm64.h | |
| parent | fd05aabce3f1191b485dbc00dd388219a1d400d2 (diff) | |
| download | coreclr-2300f42bdd35f7b971d6fbeb54d2678ea429ef34.tar.gz coreclr-2300f42bdd35f7b971d6fbeb54d2678ea429ef34.tar.bz2 coreclr-2300f42bdd35f7b971d6fbeb54d2678ea429ef34.zip | |
ARM64: Revisit for Fix GC hole in indirect call site
This fixes https://github.com/dotnet/coreclr/issues/3738.
The fix I made in
https://github.com/dotnet/coreclr/commit/4dfd323dab88b902fc9479efa60cb5d6b7659e94
used 3rd/4th operand to keep GC info, which actually conflicts with
address field which is unioned with these operands.
So, I go back to the original fix that I proposed below:
Indirect call (```br``` or ```blr```) target is encoded with a register
which the first operand internally represents.
Unfortunately, call sites use the first two operands to hold GC callee-save registers.
So, this GC register information was overridden by the call target operand
in the indirect(virtual) call sites.
The fix is to split branch instruction categories for these two instructions
while keeping ```ret``` same as before. They internally use the third
operand to encode the target since the first two are used for GC info.
The reason I didn't change ```ret``` is because the return instruction
is created as a small instruction (not using operand 3 and more).
Diffstat (limited to 'src/jit/emitfmtsarm64.h')
| -rw-r--r-- | src/jit/emitfmtsarm64.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/jit/emitfmtsarm64.h b/src/jit/emitfmtsarm64.h index a2f86ddcc5..722e48c580 100644 --- a/src/jit/emitfmtsarm64.h +++ b/src/jit/emitfmtsarm64.h @@ -118,7 +118,8 @@ IF_DEF(BI_0B, IS_NONE, JMP) // BI_0B ......iiiiiiiiii IF_DEF(BI_0C, IS_NONE, CALL) // BI_0C ......iiiiiiiiii iiiiiiiiiiiiiiii simm26:00 bl IF_DEF(BI_1A, IS_NONE, JMP) // BI_1A X.......iiiiiiii iiiiiiiiiiittttt Rt simm19:00 cbz cbnz IF_DEF(BI_1B, IS_NONE, JMP) // BI_1B B.......bbbbbiii iiiiiiiiiiittttt Rt imm6 simm14:00 tbz tbnz -IF_DEF(BR_1A, IS_NONE, CALL) // BR_1A ................ ......nnnnn..... Rn br blr ret +IF_DEF(BR_1A, IS_NONE, CALL) // BR_1A ................ ......nnnnn..... Rn ret +IF_DEF(BR_1B, IS_NONE, CALL) // BR_1B ................ ......nnnnn..... Rn br blr IF_DEF(LS_1A, IS_NONE, JMP) // LS_1A .X......iiiiiiii iiiiiiiiiiittttt Rt PC imm(1MB) IF_DEF(LS_2A, IS_NONE, NONE) // LS_2A .X.......X...... ......nnnnnttttt Rt Rn |