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| author | Steve MacLean <sdmaclea.qdt@qualcommdatacenter.com> | 2017-10-03 16:23:35 -0400 |
|---|---|---|
| committer | Steve MacLean <sdmaclea.qdt@qualcommdatacenter.com> | 2017-10-04 10:13:43 -0400 |
| commit | fba51b04114bd0a8265455e32a33fdcb087124e2 (patch) | |
| tree | 60a521d4245e0c87a77f00618a7f40a5dcd26a55 /src/jit/emitarm64.cpp | |
| parent | 375107fade072f81e011c16e8a7ac68b58ccdd03 (diff) | |
| download | coreclr-fba51b04114bd0a8265455e32a33fdcb087124e2.tar.gz coreclr-fba51b04114bd0a8265455e32a33fdcb087124e2.tar.bz2 coreclr-fba51b04114bd0a8265455e32a33fdcb087124e2.zip | |
[Arm64] Fix IF_LS_3D emitter
Diffstat (limited to 'src/jit/emitarm64.cpp')
| -rw-r--r-- | src/jit/emitarm64.cpp | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/jit/emitarm64.cpp b/src/jit/emitarm64.cpp index 374c16059a..7cd355a035 100644 --- a/src/jit/emitarm64.cpp +++ b/src/jit/emitarm64.cpp @@ -978,8 +978,12 @@ emitAttr emitter::emitInsTargetRegSize(instrDesc* id) switch (ins) { + case INS_ldxrb: case INS_ldarb: + case INS_ldaxrb: + case INS_stxrb: case INS_stlrb: + case INS_stlxrb: case INS_ldrb: case INS_strb: case INS_ldurb: @@ -987,8 +991,12 @@ emitAttr emitter::emitInsTargetRegSize(instrDesc* id) result = EA_4BYTE; break; + case INS_ldxrh: case INS_ldarh: + case INS_ldaxrh: + case INS_stxrh: case INS_stlrh: + case INS_stlxrh: case INS_ldrh: case INS_strh: case INS_ldurh: @@ -1019,8 +1027,12 @@ emitAttr emitter::emitInsTargetRegSize(instrDesc* id) result = id->idOpSize(); break; + case INS_ldxr: case INS_ldar: + case INS_ldaxr: + case INS_stxr: case INS_stlr: + case INS_stlxr: case INS_ldr: case INS_str: case INS_ldur: @@ -8994,10 +9006,14 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp) case IF_LS_3D: // LS_3D .X.......X.mmmmm ......nnnnnttttt Wm Rt Rn code = emitInsCode(ins, fmt); - code |= insEncodeDatasize(id->idOpSize()); // X - code |= insEncodeReg_Rm(id->idReg1()); // mmmmm - code |= insEncodeReg_Rt(id->idReg2()); // ttttt - code |= insEncodeReg_Rn(id->idReg2()); // nnnnn + // Arm64 store exclusive unpredictable cases + assert(id->idReg1() != id->idReg2()); + assert(id->idReg1() != id->idReg3()); + code |= insEncodeDatasizeLS(code, id->idOpSize()); // X + code |= insEncodeReg_Rm(id->idReg1()); // mmmmm + code |= insEncodeReg_Rt(id->idReg2()); // ttttt + code |= insEncodeReg_Rn(id->idReg3()); // nnnnn + dst += emitOutput_Instr(dst, code); break; case IF_DI_1A: // DI_1A X.......shiiiiii iiiiiinnnnn..... Rn imm(i12,sh) |