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author | Bruce Forstall <brucefo@microsoft.com> | 2018-06-21 13:11:13 -0700 |
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committer | Bruce Forstall <brucefo@microsoft.com> | 2018-06-21 13:11:13 -0700 |
commit | 1990fea59c19ccec643c3174b0cd5733296bb1c9 (patch) | |
tree | 9acb300bc0b702285600752911710b4a843b34b3 /src/jit/emitarm.cpp | |
parent | 6b90c5676693e826a64d15b7c507795b8ed1d98f (diff) | |
download | coreclr-1990fea59c19ccec643c3174b0cd5733296bb1c9.tar.gz coreclr-1990fea59c19ccec643c3174b0cd5733296bb1c9.tar.bz2 coreclr-1990fea59c19ccec643c3174b0cd5733296bb1c9.zip |
Fix ARM encoder limits
The ARM encoder was using slightly incorrect limits when deciding whether
a particular constant offset was allowed in an addressing mode.
Change the limits to match the instruction definitions.
Diffstat (limited to 'src/jit/emitarm.cpp')
-rw-r--r-- | src/jit/emitarm.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/jit/emitarm.cpp b/src/jit/emitarm.cpp index 81381fe25f..0ed5bceea1 100644 --- a/src/jit/emitarm.cpp +++ b/src/jit/emitarm.cpp @@ -3451,7 +3451,7 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va // Its better to fail later with a better error message than // to fail here when the RBM_OPT_RSVD is not available // - if (undisp <= 0x03fb) + if (undisp <= 0x03fc) { fmt = IF_T2_VLDST; } @@ -3466,15 +3466,15 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va } else if (emitInsIsLoadOrStore(ins)) { - if (isLowRegister(reg1) && (reg2 == REG_SP) && (ins == INS_ldr) && ((disp & 0x03fc) == disp && disp <= 0x03f8)) + if (isLowRegister(reg1) && (reg2 == REG_SP) && (ins == INS_ldr) && ((disp & 0x03fc) == disp)) { fmt = IF_T1_J2; } - else if (disp >= 0 && disp <= 0x0ffb) + else if (disp >= 0 && disp <= 0x0fff) { fmt = IF_T2_K1; } - else if (undisp <= 0x0fb) + else if (undisp <= 0x0ff) { fmt = IF_T2_H0; } @@ -3488,11 +3488,11 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va } else if (ins == INS_add) { - if (isLowRegister(reg1) && (reg2 == REG_SP) && ((disp & 0x03fc) == disp && disp <= 0x03f8)) + if (isLowRegister(reg1) && (reg2 == REG_SP) && ((disp & 0x03fc) == disp)) { fmt = IF_T1_J2; } - else if (undisp <= 0x0ffb) + else if (undisp <= 0x0fff) { if (disp < 0) { @@ -3610,7 +3610,7 @@ void emitter::emitIns_S_R(instruction ins, emitAttr attr, regNumber reg1, int va // Its better to fail later with a better error message than // to fail here when the RBM_OPT_RSVD is not available // - if (undisp <= 0x03fb) + if (undisp <= 0x03fc) { fmt = IF_T2_VLDST; } @@ -3623,15 +3623,15 @@ void emitter::emitIns_S_R(instruction ins, emitAttr attr, regNumber reg1, int va return; } } - else if (isLowRegister(reg1) && (reg2 == REG_SP) && (ins == INS_str) && ((disp & 0x03fc) == disp && disp <= 0x03f8)) + else if (isLowRegister(reg1) && (reg2 == REG_SP) && (ins == INS_str) && ((disp & 0x03fc) == disp)) { fmt = IF_T1_J2; } - else if (disp >= 0 && disp <= 0x0ffb) + else if (disp >= 0 && disp <= 0x0fff) { fmt = IF_T2_K1; } - else if (undisp <= 0x0fb) + else if (undisp <= 0x0ff) { fmt = IF_T2_H0; } |