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author | Steve MacLean, Qualcomm Datacenter Technologies, Inc <sdmaclea@qti.qualcomm.com> | 2017-05-08 15:47:22 +0000 |
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committer | Steve MacLean, Qualcomm Datacenter Technologies, Inc <sdmaclea@qti.qualcomm.com> | 2017-05-08 16:23:48 +0000 |
commit | 637c9db949076a595710a88aea9b6ff38694f8dc (patch) | |
tree | cda64961ecf964d3e25911d32330dc03206adc93 /src/jit/emit.h | |
parent | 16ca06c4b68502b39c105367f27a8f62368959d4 (diff) | |
download | coreclr-637c9db949076a595710a88aea9b6ff38694f8dc.tar.gz coreclr-637c9db949076a595710a88aea9b6ff38694f8dc.tar.bz2 coreclr-637c9db949076a595710a88aea9b6ff38694f8dc.zip |
[Arm64] Revise per comments
Diffstat (limited to 'src/jit/emit.h')
-rw-r--r-- | src/jit/emit.h | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/src/jit/emit.h b/src/jit/emit.h index c09953f328..5ec8a6af06 100644 --- a/src/jit/emit.h +++ b/src/jit/emit.h @@ -655,9 +655,6 @@ protected: // unnecessarily since the GC-ness of the second register is only needed for call instructions. // The instrDescCGCA struct's member keeping the GC-ness of the first return register is _idcSecondRetRegGCType. GCtype _idGCref : 2; // GCref operand? (value is a "GCtype") -#ifdef _TARGET_ARM64_ - GCtype _idGCref2 : 2; -#endif // Note that we use the _idReg1 and _idReg2 fields to hold // the live gcrefReg mask for the call instructions on x86/x64 @@ -671,7 +668,7 @@ protected: // x86: 30 bits // amd64: 38 bits // arm: 32 bits - // arm64: 32 bits + // arm64: 30 bits CLANG_FORMAT_COMMENT_ANCHOR; #if HAS_TINY_DESC @@ -721,8 +718,8 @@ protected: #define ID_EXTRA_BITFIELD_BITS (16) #elif defined(_TARGET_ARM64_) -// For Arm64, we have used 18 bits from the second DWORD. -#define ID_EXTRA_BITFIELD_BITS (18) +// For Arm64, we have used 16 bits from the second DWORD. +#define ID_EXTRA_BITFIELD_BITS (16) #elif defined(_TARGET_XARCH_) && !defined(LEGACY_BACKEND) // For xarch !LEGACY_BACKEND, we have used 14 bits from the second DWORD. #define ID_EXTRA_BITFIELD_BITS (14) @@ -738,7 +735,7 @@ protected: // x86: 38 bits // if HAS_TINY_DESC is not defined (which it is) // amd64: 46 bits // arm: 48 bits - // arm64: 50 bits + // arm64: 48 bits CLANG_FORMAT_COMMENT_ANCHOR; unsigned _idCnsReloc : 1; // LargeCns is an RVA and needs reloc tag @@ -751,7 +748,7 @@ protected: // x86: 40 bits // amd64: 48 bits // arm: 50 bits - // arm64: 52 bits + // arm64: 50 bits CLANG_FORMAT_COMMENT_ANCHOR; #define ID_EXTRA_BITS (ID_EXTRA_RELOC_BITS + ID_EXTRA_BITFIELD_BITS) @@ -767,7 +764,7 @@ protected: // x86: 24 bits // amd64: 16 bits // arm: 14 bits - // arm64: 12 bits + // arm64: 14 bits unsigned _idSmallCns : ID_BIT_SMALL_CNS; @@ -926,8 +923,10 @@ protected: struct { #ifdef _TARGET_ARM64_ + // For 64-bit architecture this 32-bit structure can pack with these unsigned bit fields emitLclVarAddr iiaLclVar; unsigned _idReg3Scaled : 1; // Reg3 is scaled by idOpSize bits + GCtype _idGCref2 : 2; #endif regNumber _idReg3 : REGNUM_BITS; regNumber _idReg4 : REGNUM_BITS; @@ -1081,11 +1080,15 @@ protected: #ifdef _TARGET_ARM64_ GCtype idGCrefReg2() const { - return (GCtype)_idGCref2; + assert(!idIsTiny()); + assert(!idIsSmallDsc()); + return (GCtype)idAddr()->_idGCref2; } void idGCrefReg2(GCtype gctype) { - _idGCref2 = gctype; + assert(!idIsTiny()); + assert(!idIsSmallDsc()); + idAddr()->_idGCref2 = gctype; } #endif // _TARGET_ARM64_ |