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| author | Fei Peng <fei.peng@intel.com> | 2017-10-30 11:32:08 -0700 |
|---|---|---|
| committer | Fei Peng <fei.peng@intel.com> | 2017-10-30 11:32:08 -0700 |
| commit | 5b2dcd482b3527105d3c5db24141716ff95dd855 (patch) | |
| tree | e1bdf1c77ace6b2ddb08499c577101601fb5568c /src/jit/emit.h | |
| parent | fb4af6c2908b633b200b556986815781f2139f4e (diff) | |
| download | coreclr-5b2dcd482b3527105d3c5db24141716ff95dd855.tar.gz coreclr-5b2dcd482b3527105d3c5db24141716ff95dd855.tar.bz2 coreclr-5b2dcd482b3527105d3c5db24141716ff95dd855.zip | |
Rename and simplify SSE3_4 to SSE4
Diffstat (limited to 'src/jit/emit.h')
| -rw-r--r-- | src/jit/emit.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/jit/emit.h b/src/jit/emit.h index c2b5281861..34e87b0204 100644 --- a/src/jit/emit.h +++ b/src/jit/emit.h @@ -427,7 +427,7 @@ public: #endif // DEBUG #ifdef _TARGET_XARCH_ - SetUseSSE3_4(false); + SetUseSSE4(false); SetUseAVX(false); #endif // _TARGET_XARCH_ } |