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authorKyungwoo Lee <kyulee@microsoft.com>2016-03-11 23:51:46 -0800
committerKyungwoo Lee <kyulee@microsoft.com>2016-03-15 16:36:55 -0700
commit2300f42bdd35f7b971d6fbeb54d2678ea429ef34 (patch)
tree1a22980e591deafd9557b650fb3131a79b5a55c9 /src/jit/emit.h
parentfd05aabce3f1191b485dbc00dd388219a1d400d2 (diff)
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ARM64: Revisit for Fix GC hole in indirect call site
This fixes https://github.com/dotnet/coreclr/issues/3738. The fix I made in https://github.com/dotnet/coreclr/commit/4dfd323dab88b902fc9479efa60cb5d6b7659e94 used 3rd/4th operand to keep GC info, which actually conflicts with address field which is unioned with these operands. So, I go back to the original fix that I proposed below: Indirect call (```br``` or ```blr```) target is encoded with a register which the first operand internally represents. Unfortunately, call sites use the first two operands to hold GC callee-save registers. So, this GC register information was overridden by the call target operand in the indirect(virtual) call sites. The fix is to split branch instruction categories for these two instructions while keeping ```ret``` same as before. They internally use the third operand to encode the target since the first two are used for GC info. The reason I didn't change ```ret``` is because the return instruction is created as a small instruction (not using operand 3 and more).
Diffstat (limited to 'src/jit/emit.h')
-rw-r--r--src/jit/emit.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/jit/emit.h b/src/jit/emit.h
index c35532233e..39241278a5 100644
--- a/src/jit/emit.h
+++ b/src/jit/emit.h
@@ -942,9 +942,6 @@ protected:
iiaEncodedInstrCount = (count << iaut_SHIFT) | iaut_INST_COUNT;
}
- // Note that we use the _idReg3 and _idReg4 fields to hold
- // the live gcrefReg mask for the call instructions on arm64
- //
struct
{
regNumber _idReg3 :REGNUM_BITS;