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| author | Carol Eidt <carol.eidt@microsoft.com> | 2017-11-07 17:42:55 -0800 |
|---|---|---|
| committer | Carol Eidt <carol.eidt@microsoft.com> | 2017-11-12 07:42:29 -0800 |
| commit | 01ce41954e5efa8d2de5bb9d7a0934197090a610 (patch) | |
| tree | 42c3bf276a60c2f48d3fa871b43d88e949af389d /src/jit/codegencommon.cpp | |
| parent | 102adba486f282501ce0863499ee71b59155eaac (diff) | |
| download | coreclr-01ce41954e5efa8d2de5bb9d7a0934197090a610.tar.gz coreclr-01ce41954e5efa8d2de5bb9d7a0934197090a610.tar.bz2 coreclr-01ce41954e5efa8d2de5bb9d7a0934197090a610.zip | |
ARMARCH: no cascaded adds in addr mode
On ARM and ARM64, cascaded `ADD`s in the op2 position of the root ADD are not folded into a single addressing mode. However, in `gtSetEvalOrder` it assumes that they will, so it walks both operands of the addr looking for more `ADD`s. This leads to an assert because the leaf nodes it winds up with are not the same as those returned by `genCreateAddrMode()`.
Fix #14665
Diffstat (limited to 'src/jit/codegencommon.cpp')
| -rw-r--r-- | src/jit/codegencommon.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/jit/codegencommon.cpp b/src/jit/codegencommon.cpp index 41ce431e28..d3ba991a6a 100644 --- a/src/jit/codegencommon.cpp +++ b/src/jit/codegencommon.cpp @@ -2018,7 +2018,7 @@ AGAIN: } #endif // LEGACY_BACKEND -#if defined(_TARGET_ARM64_) || (defined(_TARGET_ARM_) && !defined(LEGACY_BACKEND)) +#if defined(_TARGET_ARMARCH_) && !defined(LEGACY_BACKEND) if (cns == 0) #endif { @@ -2038,7 +2038,7 @@ AGAIN: goto AGAIN; -#if SCALED_ADDR_MODES && !defined(_TARGET_ARM64_) && !(defined(_TARGET_ARM_) && !defined(LEGACY_BACKEND)) +#if SCALED_ADDR_MODES && (!defined(_TARGET_ARMARCH_) || defined(LEGACY_BACKEND)) // TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index. case GT_MUL: if (op1->gtOverflow()) @@ -2103,7 +2103,7 @@ AGAIN: switch (op1->gtOper) { -#if !defined(_TARGET_ARM64_) && !(defined(_TARGET_ARM_) && !defined(LEGACY_BACKEND)) +#if !defined(_TARGET_ARMARCH_) || defined(LEGACY_BACKEND) // TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index. case GT_ADD: @@ -2165,7 +2165,7 @@ AGAIN: break; #endif // SCALED_ADDR_MODES -#endif // !_TARGET_ARM64_ && !(_TARGET_ARM_ && !LEGACY_BACKEND) +#endif // !_TARGET_ARMARCH || LEGACY_BACKEND case GT_NOP: @@ -2194,7 +2194,7 @@ AGAIN: noway_assert(op2); switch (op2->gtOper) { -#if !defined(_TARGET_ARM64_) && !(defined(_TARGET_ARM_) && !defined(LEGACY_BACKEND)) +#if !defined(_TARGET_ARMARCH_) || defined(LEGACY_BACKEND) // TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index. case GT_ADD: @@ -2252,7 +2252,7 @@ AGAIN: break; #endif // SCALED_ADDR_MODES -#endif // !_TARGET_ARM64_ && !(_TARGET_ARM_ && !LEGACY_BACKEND) +#endif // !_TARGET_ARMARCH || LEGACY_BACKEND case GT_NOP: |