diff options
author | Mikhail Skvortcov <m.skvortcov@partner.samsung.com> | 2017-05-23 16:25:07 +0300 |
---|---|---|
committer | Mikhail Skvortcov <m.skvortcov@partner.samsung.com> | 2017-06-05 11:30:06 +0300 |
commit | eef101ffeabd39d45240c7a12a6449f386ae3abd (patch) | |
tree | 00b3892f68c3a9a23a97ecaa30d39dd73b21fc3c /src/jit/codegenarmarch.cpp | |
parent | f1ea814c3d53387f1082cd5383ff355299269a24 (diff) | |
download | coreclr-eef101ffeabd39d45240c7a12a6449f386ae3abd.tar.gz coreclr-eef101ffeabd39d45240c7a12a6449f386ae3abd.tar.bz2 coreclr-eef101ffeabd39d45240c7a12a6449f386ae3abd.zip |
Adapt shared genLeaInstruction for arm32
Diffstat (limited to 'src/jit/codegenarmarch.cpp')
-rw-r--r-- | src/jit/codegenarmarch.cpp | 33 |
1 files changed, 25 insertions, 8 deletions
diff --git a/src/jit/codegenarmarch.cpp b/src/jit/codegenarmarch.cpp index 48e0911f8f..192d08e488 100644 --- a/src/jit/codegenarmarch.cpp +++ b/src/jit/codegenarmarch.cpp @@ -2656,7 +2656,25 @@ void CodeGen::genCodeForStoreBlk(GenTreeBlk* blkOp) } } -// produce code for a GT_LEA subnode +//------------------------------------------------------------------------ +// genScaledAdd: A helper for genLeaInstruction. +// +void CodeGen::genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale) +{ + emitter* emit = getEmitter(); +#if defined(_TARGET_ARM_) + emit->emitIns_R_R_R_I(INS_add, attr, targetReg, baseReg, indexReg, scale, INS_FLAGS_DONT_CARE, INS_OPTS_LSL); +#elif defined(_TARGET_ARM64_) + emit->emitIns_R_R_R_I(INS_add, attr, targetReg, baseReg, indexReg, scale, INS_OPTS_LSL); +#endif +} + +//------------------------------------------------------------------------ +// genLeaInstruction: Produce code for a GT_LEA node. +// +// Arguments: +// lea - the node +// void CodeGen::genLeaInstruction(GenTreeAddrMode* lea) { genConsumeOperands(lea); @@ -2664,7 +2682,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea) emitAttr size = emitTypeSize(lea); unsigned offset = lea->gtOffset; - // In ARM64 we can only load addresses of the form: + // In ARM we can only load addresses of the form: // // [Base + index*scale] // [Base + Offset] @@ -2695,12 +2713,12 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea) { regNumber tmpReg = lea->GetSingleTempReg(); - if (emitter::emitIns_valid_imm_for_add(offset, EA_8BYTE)) + if (emitter::emitIns_valid_imm_for_add(offset)) { if (lsl > 0) { // Generate code to set tmpReg = base + index*scale - emit->emitIns_R_R_R_I(INS_add, size, tmpReg, memBase->gtRegNum, index->gtRegNum, lsl, INS_OPTS_LSL); + genScaledAdd(size, tmpReg, memBase->gtRegNum, index->gtRegNum, lsl); } else // no scale { @@ -2722,7 +2740,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea) noway_assert(tmpReg != index->gtRegNum); // Then compute target reg from [tmpReg + index*scale] - emit->emitIns_R_R_R_I(INS_add, size, lea->gtRegNum, tmpReg, index->gtRegNum, lsl, INS_OPTS_LSL); + genScaledAdd(size, lea->gtRegNum, tmpReg, index->gtRegNum, lsl); } } else @@ -2730,8 +2748,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea) if (lsl > 0) { // Then compute target reg from [base + index*scale] - emit->emitIns_R_R_R_I(INS_add, size, lea->gtRegNum, memBase->gtRegNum, index->gtRegNum, lsl, - INS_OPTS_LSL); + genScaledAdd(size, lea->gtRegNum, memBase->gtRegNum, index->gtRegNum, lsl); } else { @@ -2744,7 +2761,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea) { GenTree* memBase = lea->Base(); - if (emitter::emitIns_valid_imm_for_add(offset, EA_8BYTE)) + if (emitter::emitIns_valid_imm_for_add(offset)) { if (offset != 0) { |