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author | Ben Pye <ben@curlybracket.co.uk> | 2015-07-01 15:10:09 +0100 |
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committer | Ben Pye <ben@curlybracket.co.uk> | 2015-07-24 16:45:35 +0100 |
commit | 9cd8273572260317c6acc126333e5a6e56aaeb06 (patch) | |
tree | f125e83a6908151322aa20940b63c64c621c1169 /src/jit/codegenarm.cpp | |
parent | acca43b33dcd97d1dc5d92147a3047a3bdfaf1ce (diff) | |
download | coreclr-9cd8273572260317c6acc126333e5a6e56aaeb06.tar.gz coreclr-9cd8273572260317c6acc126333e5a6e56aaeb06.tar.bz2 coreclr-9cd8273572260317c6acc126333e5a6e56aaeb06.zip |
Add ARM target for CoreCLR on Linux.
c_runtime/vprintf/test1 is disabled as casting NULL to va_list is
against the C specification.
Fix SetFilePointer tests on 32 bit platforms.
Define _FILE_OFFSET_BITS=64 so that we have long file support on 32 bit
platforms.
Implement context capture/restore for ARM.
Link libgcc_s before libunwind on ARM so C++ exceptions work.
Translate armasm to gas syntax.
Specify Thumb, VFPv3, ARMv7 for the ARM target.
Add ARM configuration to mscorlib build
Implement GetLogicalProcessorCacheSizeFromOS in PAL.
Set UNWIND_CONTEXT_IS_UCONTEXT_T from configure check.
Diffstat (limited to 'src/jit/codegenarm.cpp')
-rw-r--r-- | src/jit/codegenarm.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/jit/codegenarm.cpp b/src/jit/codegenarm.cpp index db35662f94..b3dc2d2534 100644 --- a/src/jit/codegenarm.cpp +++ b/src/jit/codegenarm.cpp @@ -778,7 +778,7 @@ void CodeGen::genCodeForBBlist() } } } -#endif _TARGET_AMD64_ +#endif //_TARGET_AMD64_ /* Do we need to generate a jump or return? */ @@ -1010,7 +1010,7 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size, getEmitter()->emitIns_R_AI(INS_lea, EA_PTR_DSP_RELOC, reg, imm); } else -#endif _TARGET_AMD64_ +#endif // _TARGET_AMD64_ { getEmitter()->emitIns_R_I(INS_mov, size, reg, imm); } |