diff options
author | Kyungwoo Lee <kyulee@microsoft.com> | 2016-04-29 10:29:28 -0700 |
---|---|---|
committer | Kyungwoo Lee <kyulee@microsoft.com> | 2016-04-29 14:52:46 -0700 |
commit | 45798f661f8c8c042f3582cde8b611d1c9c7343f (patch) | |
tree | 0d75dad9935f95c5bf4bd309899a37456e4478bd /src/inc | |
parent | 601b1051c1022d5f764224e35be59f02a6074ad0 (diff) | |
download | coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.tar.gz coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.tar.bz2 coreclr-45798f661f8c8c042f3582cde8b611d1c9c7343f.zip |
ARM64: Enabling Crossgen End-to-End Mscorlib
Fixes https://github.com/dotnet/coreclr/issues/4350
Fixes https://github.com/dotnet/coreclr/issues/4615
This is a bit large change across VM/Zap/JIT to properly support crossgen
scenario.
1. Fix incorrect `ldr` encoding with size.
2. Enforce JIT data following JIT code per method by allocating them together.
This guarantees correct PC-relative encoding for such constant data access
without fix-up.
3. For the general fix-up data acceess, use `adrp/add` instruction pairs with fix-ups.
Two more relocations types are implemented in all sides.
4. Interface dispatch stub is now implemented which is needed for
interface call for crossgen.
I've verified hello world runs with mscorlib.ni.dll.
Diffstat (limited to 'src/inc')
-rw-r--r-- | src/inc/clrnt.h | 8 | ||||
-rw-r--r-- | src/inc/utilcode.h | 36 |
2 files changed, 44 insertions, 0 deletions
diff --git a/src/inc/clrnt.h b/src/inc/clrnt.h index 9adae3770f..c15bd48fa8 100644 --- a/src/inc/clrnt.h +++ b/src/inc/clrnt.h @@ -985,6 +985,14 @@ RtlVirtualUnwind( #define IMAGE_REL_ARM64_BRANCH26 0x0003 // 26 bit offset << 2 & sign ext. for B & BL #endif +#ifndef IMAGE_REL_ARM64_PAGEBASE_REL21 +#define IMAGE_REL_ARM64_PAGEBASE_REL21 0x0004 // ADRP 21 bit PC-relative page address +#endif + +#ifndef IMAGE_REL_ARM64_PAGEOFFSET_12A +#define IMAGE_REL_ARM64_PAGEOFFSET_12A 0x0006 // ADD 12 bit page offset +#endif + #endif #endif // CLRNT_H_ diff --git a/src/inc/utilcode.h b/src/inc/utilcode.h index bb7c8bad81..fc3af0ecd5 100644 --- a/src/inc/utilcode.h +++ b/src/inc/utilcode.h @@ -4526,11 +4526,31 @@ void PutThumb2BlRel24(UINT16 * p, INT32 imm24); INT32 GetArm64Rel28(UINT32 * pCode); //***************************************************************************** +// Extract the PC-Relative page address from an adrp instruction +//***************************************************************************** +INT32 GetArm64Rel21(UINT32 * pCode); + +//***************************************************************************** +// Extract the page offset from an add instruction +//***************************************************************************** +INT32 GetArm64Rel12(UINT32 * pCode); + +//***************************************************************************** // Deposit the PC-Relative offset 'imm28' into a b or bl instruction //***************************************************************************** void PutArm64Rel28(UINT32 * pCode, INT32 imm28); //***************************************************************************** +// Deposit the PC-Relative page address 'imm21' into an adrp instruction +//***************************************************************************** +void PutArm64Rel21(UINT32 * pCode, INT32 imm21); + +//***************************************************************************** +// Deposit the page offset 'imm12' into an add instruction +//***************************************************************************** +void PutArm64Rel12(UINT32 * pCode, INT32 imm12); + +//***************************************************************************** // Returns whether the offset fits into bl instruction //***************************************************************************** inline bool FitsInThumb2BlRel24(INT32 imm24) @@ -4547,6 +4567,22 @@ inline bool FitsInRel28(INT32 val32) } //***************************************************************************** +// Returns whether the offset fits into an Arm64 adrp instruction +//***************************************************************************** +inline bool FitsInRel21(INT32 val32) +{ + return (val32 >= 0) && (val32 <= 0x001FFFFF); +} + +//***************************************************************************** +// Returns whether the offset fits into an Arm64 add instruction +//***************************************************************************** +inline bool FitsInRel12(INT32 val32) +{ + return (val32 >= 0) && (val32 <= 0x00000FFF); +} + +//***************************************************************************** // Returns whether the offset fits into an Arm64 b or bl instruction //***************************************************************************** inline bool FitsInRel28(INT64 val64) |