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| author | Gleb Balykov <g.balykov@samsung.com> | 2020-07-08 12:47:00 +0300 |
|---|---|---|
| committer | Alexander Soldatov/AI Compiler Lab /SRR/Staff Engineer/Samsung Electronics <soldatov.a@samsung.com> | 2020-07-13 18:08:49 +0300 |
| commit | 627172e192116c9a7ae9ffa47a9722ce400e83e3 (patch) | |
| tree | 7a1d099b355fe3ff7d2ed3d4d7330eef8e47a713 /packaging/coreclr.spec | |
| parent | 63c272d297e8c19e9423f3f108f488679d89be95 (diff) | |
| download | coreclr-627172e192116c9a7ae9ffa47a9722ce400e83e3.tar.gz coreclr-627172e192116c9a7ae9ffa47a9722ce400e83e3.tar.bz2 coreclr-627172e192116c9a7ae9ffa47a9722ce400e83e3.zip | |
[Tizen] Enable relocations optimizations for Tizen arm64submit/tizen/20200714.001703accepted/tizen/unified/20200714.065733
Diffstat (limited to 'packaging/coreclr.spec')
| -rwxr-xr-x | packaging/coreclr.spec | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/packaging/coreclr.spec b/packaging/coreclr.spec index f87e49acee..68d478015d 100755 --- a/packaging/coreclr.spec +++ b/packaging/coreclr.spec @@ -200,7 +200,7 @@ export CXXFLAGS+="-fstack-protector-strong" %endif %endif -%ifarch %{arm} +%ifarch %{arm} aarch64 %define _ngen_relocs_opts cmakeargs "-DFEATURE_NGEN_RELOCS_OPTIMIZATIONS=true" %else %define _ngen_relocs_opts "" |