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| author | Vyacheslav Cherkashin <v.cherkashin@samsung.com> | 2019-07-22 13:40:47 +0300 |
|---|---|---|
| committer | 이형주/Common Platform Lab(SR)/Staff Engineer/삼성전자 <leee.lee@samsung.com> | 2019-10-11 08:34:37 +0900 |
| commit | 865d7597c2476f339605bd07a3ad70f15187b0ac (patch) | |
| tree | 9166c8180129745be2427ed2fc43e65ca78b500a /THIRD-PARTY-NOTICES.TXT | |
| parent | 864c0382fe4f332b1fb4a1e6bbea81dd1172cdfc (diff) | |
| download | coreclr-865d7597c2476f339605bd07a3ad70f15187b0ac.tar.gz coreclr-865d7597c2476f339605bd07a3ad70f15187b0ac.tar.bz2 coreclr-865d7597c2476f339605bd07a3ad70f15187b0ac.zip | |
[Tizen] Implement ASan wrapper for Linux ARM32
This commit implements wrappers that allow interception transitions
from managed to external unmanaged code (CIL -> native) and back
(native -> CIL). This allows enable/disable ASan during transitions.
Due to this, we sanitize only external code, which allows us to
achieve acceptable performance.
Change-Id: I53ecdc14d28f7210cd9e7f5bd4db0c8ef5ed81fc
Signed-off-by: Vyacheslav Cherkashin <v.cherkashin@samsung.com>
Diffstat (limited to 'THIRD-PARTY-NOTICES.TXT')
0 files changed, 0 insertions, 0 deletions