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| author | Carol Eidt <carol.eidt@microsoft.com> | 2018-03-27 09:28:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-03-27 09:28:57 -0700 |
| commit | f56f7a50d60dd3ca2d8687afc492566494e6df41 (patch) | |
| tree | 69ff4e6160340072085d5c118a8976026febb269 | |
| parent | 4fca952dbf71f4aad878033d6a74a398ad676e78 (diff) | |
| parent | 399df33c3050f5636795007216f8bff0ee502a1c (diff) | |
| download | coreclr-f56f7a50d60dd3ca2d8687afc492566494e6df41.tar.gz coreclr-f56f7a50d60dd3ca2d8687afc492566494e6df41.tar.bz2 coreclr-f56f7a50d60dd3ca2d8687afc492566494e6df41.zip | |
Merge pull request #17246 from debayang/clr_jitstress_arm64
[ARM64] Fix UnspillReg instruction generation
| -rw-r--r-- | src/jit/codegenlinear.cpp | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/jit/codegenlinear.cpp b/src/jit/codegenlinear.cpp index eddec19c1f..6faaf612be 100644 --- a/src/jit/codegenlinear.cpp +++ b/src/jit/codegenlinear.cpp @@ -896,10 +896,15 @@ void CodeGen::genUnspillRegIfNeeded(GenTree* tree) inst_RV_TT(ins_Load(treeType, compiler->isSIMDTypeLocalAligned(lcl->gtLclNum)), dstReg, unspillTree); } #elif defined(_TARGET_ARM64_) - var_types targetType = unspillTree->gtType; - instruction ins = ins_Load(targetType, compiler->isSIMDTypeLocalAligned(lcl->gtLclNum)); - emitAttr attr = emitTypeSize(targetType); - emitter* emit = getEmitter(); + var_types targetType = unspillTree->gtType; + if (targetType != genActualType(varDsc->lvType) && !varTypeIsGC(targetType) && !varDsc->lvNormalizeOnLoad()) + { + assert(!varTypeIsGC(varDsc)); + targetType = genActualType(varDsc->lvType); + } + instruction ins = ins_Load(targetType, compiler->isSIMDTypeLocalAligned(lcl->gtLclNum)); + emitAttr attr = emitTypeSize(targetType); + emitter* emit = getEmitter(); // Fixes Issue #3326 attr = varTypeIsFloating(targetType) ? attr : emit->emitInsAdjustLoadStoreAttr(ins, attr); |