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author | Bruce Forstall <brucefo@microsoft.com> | 2017-05-19 15:36:41 -0700 |
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committer | GitHub <noreply@github.com> | 2017-05-19 15:36:41 -0700 |
commit | e4c36745745c62c4670be709dc6fb7941e0dcf4c (patch) | |
tree | 4efbb93b5aff03383b684fe169d17f74262bf125 | |
parent | 39a69f0002bb6758dfc76772872661f4292325f9 (diff) | |
parent | 5b99c869ca9782b6b5f4d5a28ccad239430e1d2d (diff) | |
download | coreclr-e4c36745745c62c4670be709dc6fb7941e0dcf4c.tar.gz coreclr-e4c36745745c62c4670be709dc6fb7941e0dcf4c.tar.bz2 coreclr-e4c36745745c62c4670be709dc6fb7941e0dcf4c.zip |
Merge pull request #11680 from mskvortsov/CleanupLongNYIs
[RyuJIT/ARM32] Clean up remaining GT_LONG NYIs
-rw-r--r-- | src/jit/codegenarm.cpp | 39 | ||||
-rw-r--r-- | src/jit/codegenarmarch.cpp | 5 |
2 files changed, 17 insertions, 27 deletions
diff --git a/src/jit/codegenarm.cpp b/src/jit/codegenarm.cpp index b6a749e656..7102279c83 100644 --- a/src/jit/codegenarm.cpp +++ b/src/jit/codegenarm.cpp @@ -1241,10 +1241,12 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree) // TODO-ARM-CQ: Check for the case where we can simply transfer the carry bit to a register // (signed < or >= where targetReg != REG_NA) - GenTreePtr op1 = tree->gtOp1->gtEffectiveVal(); - GenTreePtr op2 = tree->gtOp2->gtEffectiveVal(); + GenTreePtr op1 = tree->gtOp1->gtEffectiveVal(); + GenTreePtr op2 = tree->gtOp2->gtEffectiveVal(); + var_types op1Type = op1->TypeGet(); + var_types op2Type = op2->TypeGet(); - if (varTypeIsLong(op1)) + if (varTypeIsLong(op1Type)) { #ifdef DEBUG // The result of an unlowered long compare on a 32-bit target must either be @@ -1261,43 +1263,26 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree) } else { + assert(!varTypeIsLong(op2Type)); + regNumber targetReg = tree->gtRegNum; emitter* emit = getEmitter(); - emitAttr cmpAttr; genConsumeIfReg(op1); genConsumeIfReg(op2); - if (varTypeIsFloating(op1)) + if (varTypeIsFloating(op1Type)) { - assert(op1->TypeGet() == op2->TypeGet()); - instruction ins = INS_vcmp; - cmpAttr = emitTypeSize(op1->TypeGet()); - emit->emitInsBinary(ins, cmpAttr, op1, op2); + assert(op1Type == op2Type); + emit->emitInsBinary(INS_vcmp, emitTypeSize(op1Type), op1, op2); // vmrs with register 0xf has special meaning of transferring flags emit->emitIns_R(INS_vmrs, EA_4BYTE, REG_R15); } else { - var_types op1Type = op1->TypeGet(); - var_types op2Type = op2->TypeGet(); assert(!varTypeIsFloating(op2Type)); - instruction ins = INS_cmp; - if (op1Type == op2Type) - { - cmpAttr = emitTypeSize(op1Type); - } - else - { - var_types cmpType = TYP_INT; - bool op1Is64Bit = (varTypeIsLong(op1Type) || op1Type == TYP_REF); - bool op2Is64Bit = (varTypeIsLong(op2Type) || op2Type == TYP_REF); - NYI_IF(op1Is64Bit || op2Is64Bit, "Long compare"); - assert(!op1->isUsedFromMemory() || op1Type == op2Type); - assert(!op2->isUsedFromMemory() || op1Type == op2Type); - cmpAttr = emitTypeSize(cmpType); - } - emit->emitInsBinary(ins, cmpAttr, op1, op2); + var_types cmpType = (op1Type == op2Type) ? op1Type : TYP_INT; + emit->emitInsBinary(INS_cmp, emitTypeSize(cmpType), op1, op2); } // Are we evaluating this into a register? diff --git a/src/jit/codegenarmarch.cpp b/src/jit/codegenarmarch.cpp index dff745665e..e85ea6a1ca 100644 --- a/src/jit/codegenarmarch.cpp +++ b/src/jit/codegenarmarch.cpp @@ -372,6 +372,11 @@ void CodeGen::genCodeForTreeNode(GenTreePtr treeNode) genProduceReg(treeNode); break; + case GT_LONG: + assert(treeNode->isUsedFromReg()); + genConsumeRegs(treeNode); + break; + #endif // _TARGET_ARM_ case GT_IL_OFFSET: |