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authorBruce Forstall <brucefo@microsoft.com>2019-04-12 13:19:14 -0700
committerBruce Forstall <brucefo@microsoft.com>2019-04-12 13:23:58 -0700
commita9c039689e0d08ecc68783649871e9c0090ce8c3 (patch)
tree5a2919d56adafd7b5dd7434311a41418a1e4cbfb
parentf98564c3382bedf53b65689f5ea1c53942cf6729 (diff)
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Display the arm instruction size
When dumping an arm instruction, and when we don't have the actual code bytes (such as during code generation, as opposed to emission), display the (current) instruction size, either 2 bytes (2B), 4 bytes (4B), or 6 bytes (6B).
-rw-r--r--src/jit/emit.h2
-rw-r--r--src/jit/emitarm.cpp25
-rw-r--r--src/jit/emitarm64.cpp5
-rw-r--r--src/jit/emitxarch.cpp4
4 files changed, 29 insertions, 7 deletions
diff --git a/src/jit/emit.h b/src/jit/emit.h
index 1308531a90..b429920c38 100644
--- a/src/jit/emit.h
+++ b/src/jit/emit.h
@@ -1374,7 +1374,7 @@ protected:
void emitDispClsVar(CORINFO_FIELD_HANDLE fldHnd, ssize_t offs, bool reloc = false);
void emitDispFrameRef(int varx, int disp, int offs, bool asmfm);
void emitDispInsOffs(unsigned offs, bool doffs);
- void emitDispInsHex(BYTE* code, size_t sz);
+ void emitDispInsHex(instrDesc* id, BYTE* code, size_t sz);
#else // !DEBUG
#define emitVarRefOffs 0
diff --git a/src/jit/emitarm.cpp b/src/jit/emitarm.cpp
index 3d7089bb8a..9e36efb4df 100644
--- a/src/jit/emitarm.cpp
+++ b/src/jit/emitarm.cpp
@@ -6778,7 +6778,7 @@ void emitter::emitDispGC(emitAttr attr)
* Display (optionally) the instruction encoding in hex
*/
-void emitter::emitDispInsHex(BYTE* code, size_t sz)
+void emitter::emitDispInsHex(instrDesc* id, BYTE* code, size_t sz)
{
// We do not display the instruction hex if we want diff-able disassembly
if (!emitComp->opts.disDiffable)
@@ -6791,6 +6791,27 @@ void emitter::emitDispInsHex(BYTE* code, size_t sz)
{
printf(" %04X %04X", (*((unsigned short*)(code + 0))), (*((unsigned short*)(code + 2))));
}
+ else
+ {
+ assert(sz == 0);
+
+ // At least display the encoding size of the instruction, even if not displaying its actual encoding.
+ insSize isz = emitInsSize(id->idInsFmt());
+ switch (isz)
+ {
+ case ISZ_16BIT:
+ printf(" 2B");
+ break;
+ case ISZ_32BIT:
+ printf(" 4B");
+ break;
+ case ISZ_48BIT:
+ printf(" 6B");
+ break;
+ default:
+ unreached();
+ }
+ }
}
}
@@ -6822,7 +6843,7 @@ void emitter::emitDispInsHelp(
/* Display the instruction hex code */
- emitDispInsHex(code, sz);
+ emitDispInsHex(id, code, sz);
printf(" ");
diff --git a/src/jit/emitarm64.cpp b/src/jit/emitarm64.cpp
index afd5cf44e2..0345a361c8 100644
--- a/src/jit/emitarm64.cpp
+++ b/src/jit/emitarm64.cpp
@@ -10698,7 +10698,7 @@ void emitter::emitDispAddrRRExt(regNumber reg1, regNumber reg2, insOpts opt, boo
* Display (optionally) the instruction encoding in hex
*/
-void emitter::emitDispInsHex(BYTE* code, size_t sz)
+void emitter::emitDispInsHex(instrDesc* id, BYTE* code, size_t sz)
{
// We do not display the instruction hex if we want diff-able disassembly
if (!emitComp->opts.disDiffable)
@@ -10709,6 +10709,7 @@ void emitter::emitDispInsHex(BYTE* code, size_t sz)
}
else
{
+ assert(sz == 0);
printf(" ");
}
}
@@ -10742,7 +10743,7 @@ void emitter::emitDispIns(
/* Display the instruction hex code */
- emitDispInsHex(pCode, sz);
+ emitDispInsHex(id, pCode, sz);
printf(" ");
diff --git a/src/jit/emitxarch.cpp b/src/jit/emitxarch.cpp
index 6052b97493..f7b3c5baa4 100644
--- a/src/jit/emitxarch.cpp
+++ b/src/jit/emitxarch.cpp
@@ -8049,7 +8049,7 @@ void emitter::emitDispShift(instruction ins, int cnt)
* Display (optionally) the bytes for the instruction encoding in hex
*/
-void emitter::emitDispInsHex(BYTE* code, size_t sz)
+void emitter::emitDispInsHex(instrDesc* id, BYTE* code, size_t sz)
{
// We do not display the instruction hex if we want diff-able disassembly
if (!emitComp->opts.disDiffable)
@@ -8216,7 +8216,7 @@ void emitter::emitDispIns(
{
/* Display the instruction hex code */
- emitDispInsHex(code, sz);
+ emitDispInsHex(id, code, sz);
}
/* Display the instruction name */