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| author | Carol Eidt <carol.eidt@microsoft.com> | 2018-03-14 09:47:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-03-14 09:47:27 -0700 |
| commit | 23e144fa178fb2ed37da5801f7bb8ac2762aaf17 (patch) | |
| tree | 58680d470e9aa15718d00b3454401a5b3d5fa9a4 | |
| parent | 6c7447cc3488ffa212780cae1d3ef79089378e14 (diff) | |
| parent | 92f7cb29d6658c4955a8264999038fba02484f86 (diff) | |
| download | coreclr-23e144fa178fb2ed37da5801f7bb8ac2762aaf17.tar.gz coreclr-23e144fa178fb2ed37da5801f7bb8ac2762aaf17.tar.bz2 coreclr-23e144fa178fb2ed37da5801f7bb8ac2762aaf17.zip | |
Merge pull request #16853 from dotnetrt/CnvertScInt64
Fix ConvertScalarToVector128(U)Int64 codegen and improve tests
4 files changed, 13 insertions, 5 deletions
diff --git a/src/jit/hwintrinsiccodegenxarch.cpp b/src/jit/hwintrinsiccodegenxarch.cpp index 77ba37c633..58fbde8bef 100644 --- a/src/jit/hwintrinsiccodegenxarch.cpp +++ b/src/jit/hwintrinsiccodegenxarch.cpp @@ -985,8 +985,6 @@ void CodeGen::genSSE2Intrinsic(GenTreeHWIntrinsic* node) assert(op1 != nullptr); assert(op2 == nullptr); instruction ins = Compiler::insOfHWIntrinsic(intrinsicID, baseType); - // TODO-XArch-CQ -> use of type size of TYP_SIMD16 leads to - // instruction register encoding errors for SSE legacy encoding emit->emitIns_R_R(ins, emitTypeSize(baseType), targetReg, op1Reg); break; } diff --git a/src/jit/hwintrinsiclistxarch.h b/src/jit/hwintrinsiclistxarch.h index 32fa63b52a..2a43cc46a9 100644 --- a/src/jit/hwintrinsiclistxarch.h +++ b/src/jit/hwintrinsiclistxarch.h @@ -184,7 +184,7 @@ HARDWARE_INTRINSIC(SSE2_ConvertScalarToVector128Int64, "ConvertSca HARDWARE_INTRINSIC(SSE2_ConvertToVector128Single, "ConvertToVector128Single", SSE2, -1, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_cvtdq2ps, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_cvtpd2ps}, HW_Category_SimpleSIMD, HW_Flag_BaseTypeFromFirstArg|HW_Flag_NoRMWSemantics) HARDWARE_INTRINSIC(SSE2_ConvertScalarToVector128Single, "ConvertScalarToVector128Single", SSE2, -1, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_cvtsd2ss, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_SpecialCodeGen) HARDWARE_INTRINSIC(SSE2_ConvertScalarToVector128UInt32, "ConvertScalarToVector128UInt32", SSE2, -1, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_mov_i2xmm, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoRMWSemantics) -HARDWARE_INTRINSIC(SSE2_ConvertScalarToVector128UInt64, "ConvertScalarToVector128UInt64", SSE2, -1, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_mov_i2xmm, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_64BitOnly|HW_Flag_NoRMWSemantics) +HARDWARE_INTRINSIC(SSE2_ConvertScalarToVector128UInt64, "ConvertScalarToVector128UInt64", SSE2, -1, 16, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_mov_i2xmm, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_64BitOnly|HW_Flag_SpecialCodeGen|HW_Flag_NoRMWSemantics) HARDWARE_INTRINSIC(SSE2_Divide, "Divide", SSE2, -1, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_divpd}, HW_Category_SimpleSIMD, HW_Flag_NoFlag) HARDWARE_INTRINSIC(SSE2_DivideScalar, "DivideScalar", SSE2, -1, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_divsd}, HW_Category_SIMDScalar, HW_Flag_CopyUpperBits) HARDWARE_INTRINSIC(SSE2_Extract, "Extract", SSE2, -1, 16, 2, {INS_invalid, INS_invalid, INS_pextrw, INS_pextrw, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_FullRangeIMM|HW_Flag_BaseTypeFromFirstArg|HW_Flag_NoRMWSemantics) diff --git a/tests/src/JIT/HardwareIntrinsics/X86/Sse2/ConvertScalarToVector128Int64.cs b/tests/src/JIT/HardwareIntrinsics/X86/Sse2/ConvertScalarToVector128Int64.cs index eb4c5488ab..5ee35f0c17 100644 --- a/tests/src/JIT/HardwareIntrinsics/X86/Sse2/ConvertScalarToVector128Int64.cs +++ b/tests/src/JIT/HardwareIntrinsics/X86/Sse2/ConvertScalarToVector128Int64.cs @@ -52,6 +52,11 @@ namespace IntelHardwareIntrinsicTest { } + catch(Exception ex) + { + testResult = Fail; + Console.WriteLine($"{nameof(Sse2)}.{nameof(Sse2.ConvertScalarToVector128Int64)}-{ex} failed: expected PlatformNotSupportedException exception."); + } } } } diff --git a/tests/src/JIT/HardwareIntrinsics/X86/Sse2/ConvertScalarToVector128UInt64.cs b/tests/src/JIT/HardwareIntrinsics/X86/Sse2/ConvertScalarToVector128UInt64.cs index f75cc86aea..361f98eaf2 100644 --- a/tests/src/JIT/HardwareIntrinsics/X86/Sse2/ConvertScalarToVector128UInt64.cs +++ b/tests/src/JIT/HardwareIntrinsics/X86/Sse2/ConvertScalarToVector128UInt64.cs @@ -26,10 +26,10 @@ namespace IntelHardwareIntrinsicTest { if (Environment.Is64BitProcess) { - var vd = Sse2.ConvertScalarToVector128UInt64((ulong)5); + var vd = Sse2.ConvertScalarToVector128UInt64(0xffffffff01ul); Unsafe.Write(ulongTable.outArrayPtr, vd); - if (!ulongTable.CheckResult((x, y) => (y[0] == 5) && (y[1] == 0))) + if (!ulongTable.CheckResult((x, y) => (y[0] == 0xffffffff01ul) && (y[1] == 0))) { Console.WriteLine("SSE ConvertScalarToVector128Single failed on ulong:"); foreach (var item in ulongTable.outArray) @@ -52,6 +52,11 @@ namespace IntelHardwareIntrinsicTest { } + catch(Exception ex) + { + testResult = Fail; + Console.WriteLine($"{nameof(Sse2)}.{nameof(Sse2.ConvertScalarToVector128UInt64)}-{ex} failed: expected PlatformNotSupportedException exception."); + } } } } |