summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMichelle McDaniel <adiaaida@gmail.com>2016-05-13 08:35:23 -0700
committerMichelle McDaniel <adiaaida@gmail.com>2016-05-16 09:11:03 -0700
commitf11e4f4f49162e33e46614c4d3a3c36584eca2f4 (patch)
tree0a7015969eeddb935ae7ce77bba26f1eb4b8809e
parent71fe847d72f7b6a4d019c3bd2715ceba3bc1b33b (diff)
downloadcoreclr-f11e4f4f49162e33e46614c4d3a3c36584eca2f4.tar.gz
coreclr-f11e4f4f49162e33e46614c4d3a3c36584eca2f4.tar.bz2
coreclr-f11e4f4f49162e33e46614c4d3a3c36584eca2f4.zip
Disable RegPair for x86 Longs
We are not using regpairs for longs on x86 ryujit, so we need to turn off CPU_LONG_USES_REGPAIR. This is the first step to getting var = call for GT_CALLs with long return types on x86.
-rw-r--r--src/jit/codegenxarch.cpp2
-rw-r--r--src/jit/gentree.cpp4
-rw-r--r--src/jit/instr.cpp13
-rw-r--r--src/jit/target.h9
4 files changed, 20 insertions, 8 deletions
diff --git a/src/jit/codegenxarch.cpp b/src/jit/codegenxarch.cpp
index 6e32376d7a..506e1e60ed 100644
--- a/src/jit/codegenxarch.cpp
+++ b/src/jit/codegenxarch.cpp
@@ -1837,8 +1837,6 @@ CodeGen::genCodeForTreeNode(GenTreePtr treeNode)
{
// All long enregistered nodes will have been decomposed into their
// constituent lo and hi nodes.
- regPairNo targetPair = treeNode->gtRegPair;
- noway_assert(targetPair == REG_PAIR_NONE);
targetReg = REG_NA;
}
else
diff --git a/src/jit/gentree.cpp b/src/jit/gentree.cpp
index 8d7296a3a1..55fa724bae 100644
--- a/src/jit/gentree.cpp
+++ b/src/jit/gentree.cpp
@@ -1103,7 +1103,7 @@ Compiler::fgWalkResult Compiler::fgWalkTree(GenTreePtr * pTree,
void
GenTree::gtClearReg(Compiler* compiler)
{
-#if !defined(LEGACY_BACKEND) && !defined(_TARGET_64BIT_)
+#if CPU_LONG_USES_REGPAIR
if (isRegPairType(TypeGet()) ||
// (IsLocal() && isRegPairType(compiler->lvaTable[gtLclVarCommon.gtLclNum].TypeGet())) ||
(OperGet() == GT_MUL && (gtFlags & GTF_MUL_64RSLT)))
@@ -1111,7 +1111,7 @@ GenTree::gtClearReg(Compiler* compiler)
gtRegPair = REG_PAIR_NONE;
}
else
-#endif // !defined(LEGACY_BACKEND) && !defined(_TARGET_64BIT_)
+#endif // CPU_LONG_USES_REGPAIR
{
gtRegNum = REG_NA;
}
diff --git a/src/jit/instr.cpp b/src/jit/instr.cpp
index 40904b3075..3dd10f2d2d 100644
--- a/src/jit/instr.cpp
+++ b/src/jit/instr.cpp
@@ -1483,7 +1483,7 @@ AGAIN:
assert(!instIsFP(ins));
-#ifndef _TARGET_64BIT_
+#if CPU_LONG_USES_REGPAIR
if (tree->gtType == TYP_LONG)
{
if (offs)
@@ -1497,7 +1497,7 @@ AGAIN:
}
}
else
-#endif // !_TARGET_64BIT_
+#endif // CPU_LONG_USES_REGPAIR
{
reg = tree->gtRegNum;
}
@@ -1663,6 +1663,8 @@ AGAIN:
#ifdef _TARGET_XARCH_
assert(!instIsFP(ins));
#endif
+
+#if CPU_LONG_USES_REGPAIR
if (tree->gtType == TYP_LONG)
{
if (offs)
@@ -1676,6 +1678,7 @@ AGAIN:
}
}
else
+#endif // CPU_LONG_USES_REGPAIR
{
rg2 = tree->gtRegNum;
}
@@ -1899,7 +1902,7 @@ LONGREG_TT_IV:
assert(instIsFP(ins) == 0);
-#ifndef _TARGET_64BIT_
+#if CPU_LONG_USES_REGPAIR
if (tree->gtType == TYP_LONG)
{
if (offs == 0)
@@ -1921,7 +1924,7 @@ LONGREG_TT_IV:
#endif
}
else
-#endif // !_TARGET_64BIT_
+#endif // CPU_LONG_USES_REGPAIR
{
reg = tree->gtRegNum;
}
@@ -2347,6 +2350,7 @@ LONGREG_RVTT:
regNumber rg2;
+#if CPU_LONG_USES_REGPAIR
if (tree->gtType == TYP_LONG)
{
if (offs)
@@ -2361,6 +2365,7 @@ LONGREG_RVTT:
}
}
else
+#endif // LEGACY_BACKEND
{
rg2 = tree->gtRegNum;
}
diff --git a/src/jit/target.h b/src/jit/target.h
index 4810dfe690..cd03315206 100644
--- a/src/jit/target.h
+++ b/src/jit/target.h
@@ -337,7 +337,16 @@ typedef unsigned short regPairNoSmall; // arm: need 12 bits
#if defined(_TARGET_X86_)
#define CPU_LOAD_STORE_ARCH 0
+
+#ifdef LEGACY_BACKEND
#define CPU_LONG_USES_REGPAIR 1
+#else
+ #define CPU_LONG_USES_REGPAIR 0 // RyuJIT x86 doesn't use the regPairNo field to record register pairs for long
+ // type tree nodes, and instead either decomposes them (for non-atomic operations)
+ // or stores multiple regNumber values for operations such as calls where the
+ // register definitions are effectively "atomic".
+#endif // LEGACY_BACKEND
+
#define CPU_HAS_FP_SUPPORT 1
#define ROUND_FLOAT 1 // round intermed float expression results
#define CPU_HAS_BYTE_REGS 1