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| author | Tanner Gooding <tagoo@outlook.com> | 2018-11-29 07:59:27 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-11-29 07:59:27 -0800 |
| commit | 5feb0389f1e1ba715fba5560c979ac6362b1bcf8 (patch) | |
| tree | efd6472e6c1182252ad797f59ded9d63cb25e9ac | |
| parent | 40bf810b5cb83ba45008f9f8c12a4e3d46eb6832 (diff) | |
| download | coreclr-5feb0389f1e1ba715fba5560c979ac6362b1bcf8.tar.gz coreclr-5feb0389f1e1ba715fba5560c979ac6362b1bcf8.tar.bz2 coreclr-5feb0389f1e1ba715fba5560c979ac6362b1bcf8.zip | |
Updating genSIMDZero to only use `xorps` (#21249)
| -rw-r--r-- | src/jit/simdcodegenxarch.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/jit/simdcodegenxarch.cpp b/src/jit/simdcodegenxarch.cpp index c0ecf25cb7..0fd2d1577a 100644 --- a/src/jit/simdcodegenxarch.cpp +++ b/src/jit/simdcodegenxarch.cpp @@ -730,9 +730,11 @@ void CodeGen::genSIMDScalarMove( void CodeGen::genSIMDZero(var_types targetType, var_types baseType, regNumber targetReg) { - // pxor reg, reg - instruction ins = getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseXor, baseType); - inst_RV_RV(ins, targetReg, targetReg, targetType, emitActualTypeSize(targetType)); + // We just use `INS_xorps` instead of `getOpForSIMDIntrinsic(SIMDIntrinsicBitwiseXor, baseType)` + // since `genSIMDZero` is used for both `System.Numerics.Vectors` and HardwareIntrinsics. Modern + // CPUs handle this specially in the renamer and it never hits the execution pipeline, additionally + // `INS_xorps` is always available (when using either the legacy or VEX encoding). + inst_RV_RV(INS_xorps, targetReg, targetReg, targetType, emitActualTypeSize(targetType)); } //------------------------------------------------------------------------ |