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authorPrayag Verma <prayag.verma@gmail.com>2016-02-18 04:43:34 (GMT)
committerPrayag Verma <prayag.verma@gmail.com>2016-02-18 04:43:34 (GMT)
commitd957481d072a434dfd116ac2255180e09c86fac5 (patch)
treee77c718f8f70a719185783e06d0f998628fd5105
parent0c89b38b142ba1bb3f2339e55c9aecc47447f876 (diff)
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Fix a typo in docs
`peformance` → `performance`
-rw-r--r--docs/multigpu.md2
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/multigpu.md b/docs/multigpu.md
index 01cfb89..d91acef 100644
--- a/docs/multigpu.md
+++ b/docs/multigpu.md
@@ -17,7 +17,7 @@ updated model, 0\-\>2, and then 0\-\>1, 2\-\>3.
For best performance, P2P DMA access between devices is needed. Without P2P access, for example crossing PCIe root complex, data is copied through host and effective exchange bandwidth is greatly reduced.
-Current implementation has a "soft" assumption that the devices being used are homogeneous. In practice, any devices of the same general class should work together, but performance and total size is limited by the smallest device being used. e.g. if you combine a TitanX and a GTX980, peformance will be limited by the 980. Mixing vastly different levels of boards, e.g. Kepler and Fermi, is not supported.
+Current implementation has a "soft" assumption that the devices being used are homogeneous. In practice, any devices of the same general class should work together, but performance and total size is limited by the smallest device being used. e.g. if you combine a TitanX and a GTX980, performance will be limited by the 980. Mixing vastly different levels of boards, e.g. Kepler and Fermi, is not supported.
"nvidia-smi topo -m" will show you the connectivity matrix. You can do P2P through PCIe bridges, but not across socket level links at this time, e.g. across CPU sockets on a multi-socket motherboard.