Imported Upstream version 1.62.0upstream/1.62.0

Change-Id: I9d4c1ddb7b7d8f0069217ecc582700f9fda6dd4c
Signed-off-by: DongHun Kwak <dh0128.kwak@samsung.com>

6 files changed, 37 insertions, 10 deletions

diff --git a/boost/atomic/detail/caps_gcc_x86.hpp b/boost/atomic/detail/caps_gcc_x86.hpp
index 0696bf1d2f..7485b010c7 100644
--- a/boost/atomic/detail/caps_gcc_x86.hpp
+++ b/boost/atomic/detail/caps_gcc_x86.hpp
@@ -22,6 +22,8 @@
 #pragma once
 #endif
 
+#if defined(__GNUC__)
+
 #if defined(__i386__) &&\
     (\
         defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) ||\
@@ -35,6 +37,27 @@
 #define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B 1
 #endif
 
+#if defined(__x86_64__) || defined(__SSE2__)
+// Use mfence only if SSE2 is available
+#define BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE 1
+#endif
+
+#else // defined(__GNUC__)
+
+#if defined(__i386__) && !defined(BOOST_ATOMIC_NO_CMPXCHG8B)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG8B 1
+#endif
+
+#if defined(__x86_64__) && !defined(BOOST_ATOMIC_NO_CMPXCHG16B)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B 1
+#endif
+
+#if !defined(BOOST_ATOMIC_NO_MFENCE)
+#define BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE 1
+#endif
+
+#endif // defined(__GNUC__)
+
 #define BOOST_ATOMIC_INT8_LOCK_FREE 2
 #define BOOST_ATOMIC_INT16_LOCK_FREE 2
 #define BOOST_ATOMIC_INT32_LOCK_FREE 2
diff --git a/boost/atomic/detail/caps_msvc_x86.hpp b/boost/atomic/detail/caps_msvc_x86.hpp
index 5661a5b7ab..2ee4c92111 100644
--- a/boost/atomic/detail/caps_msvc_x86.hpp
+++ b/boost/atomic/detail/caps_msvc_x86.hpp
@@ -30,6 +30,11 @@
 #define BOOST_ATOMIC_DETAIL_X86_HAS_CMPXCHG16B 1
 #endif
 
+#if defined(_MSC_VER) && (defined(_M_AMD64) || (defined(_M_IX86) && defined(_M_IX86_FP) && _M_IX86_FP >= 2))
+// Use mfence only if SSE2 is available
+#define BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE 1
+#endif
+
 #define BOOST_ATOMIC_INT8_LOCK_FREE 2
 #define BOOST_ATOMIC_INT16_LOCK_FREE 2
 #define BOOST_ATOMIC_INT32_LOCK_FREE 2
diff --git a/boost/atomic/detail/ops_gcc_sparc.hpp b/boost/atomic/detail/ops_gcc_sparc.hpp
index 020882bbfa..faefecaf76 100644
--- a/boost/atomic/detail/ops_gcc_sparc.hpp
+++ b/boost/atomic/detail/ops_gcc_sparc.hpp
@@ -66,7 +66,7 @@ struct gcc_sparc_cas32 :
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        fence_before_store(order);
+        fence_before(order);
         storage = v;
         fence_after_store(order);
     }
@@ -107,7 +107,7 @@ struct gcc_sparc_cas32 :
 
     static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        base_type::fence_before(order);
+        fence_before(order);
         __asm__ __volatile__
         (
             "swap [%1], %0"
@@ -115,7 +115,7 @@ struct gcc_sparc_cas32 :
             : "r" (&storage)
             : "memory"
         );
-        base_type::fence_after(order);
+        fence_after(order);
         return v;
     }
 
@@ -152,7 +152,7 @@ struct gcc_sparc_cas64 :
 
     static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
     {
-        fence_before_store(order);
+        fence_before(order);
         storage = v;
         fence_after_store(order);
     }
diff --git a/boost/atomic/detail/ops_gcc_x86.hpp b/boost/atomic/detail/ops_gcc_x86.hpp
index f68125c491..a4e4af3660 100644
--- a/boost/atomic/detail/ops_gcc_x86.hpp
+++ b/boost/atomic/detail/ops_gcc_x86.hpp
@@ -485,7 +485,7 @@ BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
     {
         __asm__ __volatile__
         (
-#if defined(__x86_64__) || defined(__SSE2__)
+#if defined(BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE)
             "mfence\n"
 #else
             "lock; addl $0, (%%esp)\n"
diff --git a/boost/atomic/detail/ops_msvc_x86.hpp b/boost/atomic/detail/ops_msvc_x86.hpp
index 589c029864..04b496efb6 100644
--- a/boost/atomic/detail/ops_msvc_x86.hpp
+++ b/boost/atomic/detail/ops_msvc_x86.hpp
@@ -42,7 +42,7 @@
 #pragma warning(disable: 4731)
 #endif
 
-#if defined(_MSC_VER) && (defined(_M_AMD64) || (defined(_M_IX86) && defined(_M_IX86_FP) && _M_IX86_FP >= 2))
+#if defined(BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE)
 extern "C" void _mm_mfence(void);
 #if defined(BOOST_MSVC)
 #pragma intrinsic(_mm_mfence)
@@ -74,8 +74,7 @@ struct msvc_x86_operations_base
 {
     static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
     {
-#if defined(_MSC_VER) && (defined(_M_AMD64) || (defined(_M_IX86) && defined(_M_IX86_FP) && _M_IX86_FP >= 2))
-        // Use mfence only if SSE2 is available
+#if defined(BOOST_ATOMIC_DETAIL_X86_HAS_MFENCE)
         _mm_mfence();
 #else
         long tmp;
diff --git a/boost/atomic/detail/platform.hpp b/boost/atomic/detail/platform.hpp
index b6c48ef0f9..34be8e6a0a 100644
--- a/boost/atomic/detail/platform.hpp
+++ b/boost/atomic/detail/platform.hpp
@@ -43,7 +43,7 @@
 
 #define BOOST_ATOMIC_DETAIL_PLATFORM gcc_atomic
 
-#elif defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
+#elif (defined(__GNUC__) || defined(__SUNPRO_CC)) && (defined(__i386__) || defined(__x86_64__))
 
 #define BOOST_ATOMIC_DETAIL_PLATFORM gcc_x86
 
@@ -65,7 +65,7 @@
 
 #define BOOST_ATOMIC_DETAIL_PLATFORM gcc_arm
 
-#elif defined(__GNUC__) && defined(__sparc_v9__)
+#elif (defined(__GNUC__) || defined(__SUNPRO_CC)) && (defined(__sparcv8plus) || defined(__sparc_v9__))
 
 #define BOOST_ATOMIC_DETAIL_PLATFORM gcc_sparc