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| author | Richard Earnshaw <richard.earnshaw@arm.com> | 2002-01-19 12:27:24 +0000 |
|---|---|---|
| committer | Richard Earnshaw <richard.earnshaw@arm.com> | 2002-01-19 12:27:24 +0000 |
| commit | a2fc1b1f19d4d4853d78d0c7bf7ed42e06cbb8a1 (patch) | |
| tree | 3fd103c5cef719a6a309d1bc96e20be6c5d61b11 /opcodes | |
| parent | 140f998426704f8ef286f58033ab983850d39552 (diff) | |
| download | binutils-a2fc1b1f19d4d4853d78d0c7bf7ed42e06cbb8a1.tar.gz binutils-a2fc1b1f19d4d4853d78d0c7bf7ed42e06cbb8a1.tar.bz2 binutils-a2fc1b1f19d4d4853d78d0c7bf7ed42e06cbb8a1.zip | |
* arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h.
* arm-dis.c (print_insn_arm): Don't handle 'h' case.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 7 | ||||
| -rw-r--r-- | opcodes/arm-opc.h | 5 |
3 files changed, 7 insertions, 10 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 37fcea5bebc..3caef39bd18 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2002-01-19 Richard Earnshaw <rearnsha@arm.com> + + * arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h. + * arm-dis.c (print_insn_arm): Don't handle 'h' case. + 2002-01-18 Keith Walker <keith.walker@arm.com> * arm-opc.h (arm_opcodes): Add bxj instruction. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index b2807c5325a..7e9b3309008 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -390,13 +390,6 @@ print_insn_arm (pc, info, given) func (stream, "t"); break; - case 'h': - if ((given & 0x00000020) == 0x00000020) - func (stream, "h"); - else - func (stream, "b"); - break; - case 'A': func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h index 34d3b309fe8..85f611d1a00 100644 --- a/opcodes/arm-opc.h +++ b/opcodes/arm-opc.h @@ -51,7 +51,6 @@ struct thumb_opcode %<bitnum>?ab print a if bit is one else print b %p print 'p' iff bits 12-15 are 15 %t print 't' iff bit 21 set and bit 24 clear - %h print 'h' iff bit 5 set, else print 'b' %o print operand2 (immediate or register + shift) %a print address for ldr/str instruction %s print address for ldr/str halfword/signextend instruction @@ -146,8 +145,8 @@ static struct arm_opcode arm_opcodes[] = {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, /* ARM Instructions. */ - {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"}, - {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"}, + {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, + {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, |