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| author | Sangmin Seo <sangmin7.seo@samsung.com> | 2017-07-11 19:45:45 +0900 |
|---|---|---|
| committer | Slava Barinov <v.barinov@samsung.com> | 2019-12-16 15:28:16 +0300 |
| commit | b01afcb4aa2777698386bdcf68110d1b5e25397f (patch) | |
| tree | 286d8644a6994b998c9daf347e6ebac9b6af11f4 | |
| parent | d62f66999f8f33054bd1c37fc5522aa0938fa306 (diff) | |
| download | binutils-b01afcb4aa2777698386bdcf68110d1b5e25397f.tar.gz binutils-b01afcb4aa2777698386bdcf68110d1b5e25397f.tar.bz2 binutils-b01afcb4aa2777698386bdcf68110d1b5e25397f.zip | |
ASan build fix: resolve multiple definitions.
Put "extern" to multiply-defined variables in order to make
-fno-common work.
Change-Id: Ib5a882e3c536d868e8098e385823e50ac78f2d21
| -rw-r--r-- | sim/arm/armemu.c | 2 | ||||
| -rw-r--r-- | sim/arm/armsupp.c | 2 | ||||
| -rw-r--r-- | sim/arm/maverick.c | 6 |
3 files changed, 6 insertions, 4 deletions
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 76f398b3d71..e7ba96639e7 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -1142,7 +1142,7 @@ handle_VFP_move (ARMul_State * state, ARMword instr) /* The PC pipeline value depends on whether ARM or Thumb instructions are being executed. */ -ARMword isize; +extern ARMword isize; ARMword #ifdef MODE32 diff --git a/sim/arm/armsupp.c b/sim/arm/armsupp.c index 11bb53c5b70..a07b162554f 100644 --- a/sim/arm/armsupp.c +++ b/sim/arm/armsupp.c @@ -22,6 +22,8 @@ /* Definitions for the support routines. */ +ARMword isize; + static ARMword ModeToBank (ARMword); static void EnvokeList (ARMul_State *, unsigned long, unsigned long); diff --git a/sim/arm/maverick.c b/sim/arm/maverick.c index c1126921290..c00908cf551 100644 --- a/sim/arm/maverick.c +++ b/sim/arm/maverick.c @@ -60,9 +60,9 @@ union maverick_acc_regs long double ld; /* Acc registers are 72-bits. */ }; -struct maverick_regs DSPregs[16]; -union maverick_acc_regs DSPacc[4]; -ARMword DSPsc; +extern struct maverick_regs DSPregs[16]; +extern union maverick_acc_regs DSPacc[4]; +extern ARMword DSPsc; #define DEST_REG (BITS (12, 15)) #define SRC1_REG (BITS (16, 19)) |