From e65c5d143fd1fc7e4415889525a521db811946e6 Mon Sep 17 00:00:00 2001 From: Ben Ashbaugh Date: Mon, 6 Mar 2023 17:02:40 -0800 Subject: headers support for SPV_INTEL_bfloat16_conversion --- include/spirv/unified1/spirv.bf | 3 +++ include/spirv/unified1/spirv.core.grammar.json | 30 ++++++++++++++++++++++++++ include/spirv/unified1/spirv.cs | 3 +++ include/spirv/unified1/spirv.h | 5 +++++ include/spirv/unified1/spirv.hpp | 5 +++++ include/spirv/unified1/spirv.hpp11 | 5 +++++ include/spirv/unified1/spirv.json | 3 +++ include/spirv/unified1/spirv.lua | 3 +++ include/spirv/unified1/spirv.py | 3 +++ include/spirv/unified1/spv.d | 3 +++ 10 files changed, 63 insertions(+) (limited to 'include/spirv') diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf index 946e236..39d32fc 100644 --- a/include/spirv/unified1/spirv.bf +++ b/include/spirv/unified1/spirv.bf @@ -1147,6 +1147,7 @@ namespace Spv OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, FPGAKernelAttributesv2INTEL = 6161, FPGAArgumentInterfacesINTEL = 6174, @@ -1953,6 +1954,8 @@ namespace Spv OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json index a43dfec..ee94b81 100644 --- a/include/spirv/unified1/spirv.core.grammar.json +++ b/include/spirv/unified1/spirv.core.grammar.json @@ -9043,6 +9043,30 @@ "capabilities" : [ "LongConstantCompositeINTEL" ], "version" : "None" }, + { + "opname" : "OpConvertFToBF16INTEL", + "class" : "Conversion", + "opcode" : 6116, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'Float Value'" } + ], + "capabilities" : [ "BFloat16ConversionINTEL" ], + "version" : "None" + }, + { + "opname" : "OpConvertBF16ToFINTEL", + "class" : "Conversion", + "opcode" : 6117, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'BFloat16 Value'" } + ], + "capabilities" : [ "BFloat16ConversionINTEL" ], + "version" : "None" + }, { "opname" : "OpControlBarrierArriveINTEL", "class" : "Barrier", @@ -14896,6 +14920,12 @@ "extensions" : [ "SPV_INTEL_debug_module" ], "version" : "None" }, + { + "enumerant" : "BFloat16ConversionINTEL", + "value" : 6115, + "extensions" : [ "SPV_INTEL_bfloat16_conversion" ], + "version" : "None" + }, { "enumerant" : "SplitBarrierINTEL", "value" : 6141, diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs index d30c0fe..0ab9c68 100644 --- a/include/spirv/unified1/spirv.cs +++ b/include/spirv/unified1/spirv.cs @@ -1146,6 +1146,7 @@ namespace Spv OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, FPGAKernelAttributesv2INTEL = 6161, FPGAArgumentInterfacesINTEL = 6174, @@ -1952,6 +1953,8 @@ namespace Spv OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h index d7d1ec0..05cbb46 100644 --- a/include/spirv/unified1/spirv.h +++ b/include/spirv/unified1/spirv.h @@ -1146,6 +1146,7 @@ typedef enum SpvCapability_ { SpvCapabilityOptNoneINTEL = 6094, SpvCapabilityAtomicFloat16AddEXT = 6095, SpvCapabilityDebugInfoModuleINTEL = 6114, + SpvCapabilityBFloat16ConversionINTEL = 6115, SpvCapabilitySplitBarrierINTEL = 6141, SpvCapabilityFPGAKernelAttributesv2INTEL = 6161, SpvCapabilityFPGAArgumentInterfacesINTEL = 6174, @@ -1950,6 +1951,8 @@ typedef enum SpvOp_ { SpvOpTypeStructContinuedINTEL = 6090, SpvOpConstantCompositeContinuedINTEL = 6091, SpvOpSpecConstantCompositeContinuedINTEL = 6092, + SpvOpConvertFToBF16INTEL = 6116, + SpvOpConvertBF16ToFINTEL = 6117, SpvOpControlBarrierArriveINTEL = 6142, SpvOpControlBarrierWaitINTEL = 6143, SpvOpGroupIMulKHR = 6401, @@ -2653,6 +2656,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp index 2036ede..0620387 100644 --- a/include/spirv/unified1/spirv.hpp +++ b/include/spirv/unified1/spirv.hpp @@ -1142,6 +1142,7 @@ enum Capability { CapabilityOptNoneINTEL = 6094, CapabilityAtomicFloat16AddEXT = 6095, CapabilityDebugInfoModuleINTEL = 6114, + CapabilityBFloat16ConversionINTEL = 6115, CapabilitySplitBarrierINTEL = 6141, CapabilityFPGAKernelAttributesv2INTEL = 6161, CapabilityFPGAArgumentInterfacesINTEL = 6174, @@ -1946,6 +1947,8 @@ enum Op { OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, @@ -2649,6 +2652,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 index 9cebc8d..12236d0 100644 --- a/include/spirv/unified1/spirv.hpp11 +++ b/include/spirv/unified1/spirv.hpp11 @@ -1142,6 +1142,7 @@ enum class Capability : unsigned { OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, FPGAKernelAttributesv2INTEL = 6161, FPGAArgumentInterfacesINTEL = 6174, @@ -1946,6 +1947,8 @@ enum class Op : unsigned { OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, @@ -2649,6 +2652,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json index b4b1233..5fa3383 100644 --- a/include/spirv/unified1/spirv.json +++ b/include/spirv/unified1/spirv.json @@ -1122,6 +1122,7 @@ "OptNoneINTEL": 6094, "AtomicFloat16AddEXT": 6095, "DebugInfoModuleINTEL": 6114, + "BFloat16ConversionINTEL": 6115, "SplitBarrierINTEL": 6141, "FPGAKernelAttributesv2INTEL": 6161, "FPGAArgumentInterfacesINTEL": 6174, @@ -1936,6 +1937,8 @@ "OpTypeStructContinuedINTEL": 6090, "OpConstantCompositeContinuedINTEL": 6091, "OpSpecConstantCompositeContinuedINTEL": 6092, + "OpConvertFToBF16INTEL": 6116, + "OpConvertBF16ToFINTEL": 6117, "OpControlBarrierArriveINTEL": 6142, "OpControlBarrierWaitINTEL": 6143, "OpGroupIMulKHR": 6401, diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua index 388dee0..557ac5e 100644 --- a/include/spirv/unified1/spirv.lua +++ b/include/spirv/unified1/spirv.lua @@ -1104,6 +1104,7 @@ spv = { OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, FPGAKernelAttributesv2INTEL = 6161, FPGAArgumentInterfacesINTEL = 6174, @@ -1897,6 +1898,8 @@ spv = { OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py index 3dd21f2..b97bcbb 100644 --- a/include/spirv/unified1/spirv.py +++ b/include/spirv/unified1/spirv.py @@ -1104,6 +1104,7 @@ spv = { 'OptNoneINTEL' : 6094, 'AtomicFloat16AddEXT' : 6095, 'DebugInfoModuleINTEL' : 6114, + 'BFloat16ConversionINTEL' : 6115, 'SplitBarrierINTEL' : 6141, 'FPGAKernelAttributesv2INTEL' : 6161, 'FPGAArgumentInterfacesINTEL' : 6174, @@ -1897,6 +1898,8 @@ spv = { 'OpTypeStructContinuedINTEL' : 6090, 'OpConstantCompositeContinuedINTEL' : 6091, 'OpSpecConstantCompositeContinuedINTEL' : 6092, + 'OpConvertFToBF16INTEL' : 6116, + 'OpConvertBF16ToFINTEL' : 6117, 'OpControlBarrierArriveINTEL' : 6142, 'OpControlBarrierWaitINTEL' : 6143, 'OpGroupIMulKHR' : 6401, diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d index 04e84cd..6f542aa 100644 --- a/include/spirv/unified1/spv.d +++ b/include/spirv/unified1/spv.d @@ -1149,6 +1149,7 @@ enum Capability : uint OptNoneINTEL = 6094, AtomicFloat16AddEXT = 6095, DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, SplitBarrierINTEL = 6141, FPGAKernelAttributesv2INTEL = 6161, FPGAArgumentInterfacesINTEL = 6174, @@ -1955,6 +1956,8 @@ enum Op : uint OpTypeStructContinuedINTEL = 6090, OpConstantCompositeContinuedINTEL = 6091, OpSpecConstantCompositeContinuedINTEL = 6092, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, OpControlBarrierArriveINTEL = 6142, OpControlBarrierWaitINTEL = 6143, OpGroupIMulKHR = 6401, -- cgit v1.2.3