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2023-10-04Add a Source Language for Slang (#383)upstream/1.3.268upstreampradyumans10-1/+15
* Add a Source Language for Slang * Changed src lang name from SLANG to Slang
2023-09-20Add LiteralFloat to operand_kinds (#380)Fabian Wahlster1-0/+5
LiteralFloat was introduced with FPMaxErrorDecorationINTEL, but no entry in operand_kinds corresponds to it
2023-09-20Add headers for SPV_NV_displacement_micromap. (#374)alelenv10-0/+148
* Add headers for SPV_NV_displacement_micromap. * Review feedback 1 Co-authored-by: alan-baker <alanbaker@google.com> --------- Co-authored-by: alan-baker <alanbaker@google.com>
2023-09-20remove additional version "1.0" from SecondaryViewportRelativeNV (#379)Fabian Wahlster1-2/+1
SecondaryViewportRelativeNV already has a version field
2023-09-13Remove Kernel from ConstantSampler enum values (#378)gnl211-7/+0
These can only be used with OpConstantSampler, so they are naturally restricted from being used in places where they're not supported.
2023-09-13Add SPV_INTEL_cache_controls extension support (#376)Andrzej Ratajewski10-2/+276
Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_cache_controls.asciidoc
2023-08-23Validate enums have sensible versions and are visible (#369)David Neto1-673/+1349
* Validate enums have a sensible versions and are visible Add version field for each eumerant. For capabilities and instructions introduced by an extension (its first version is "None"): - the capability should be guarded by an extension - the instruction should be guarded by a capability. Other enums are presumed guarded transitiviely by use as an operand to an instruction or another operand. Fixes: #278, #368 * Fix capability logic, and check more cases For capabilities, only check for lack of an extension. If capability X lists capabilities Y and Z, those are not guards *for* X, but rather when X is enabled it also implicitly enables Y and Z. Also, an instruction that is *not* in a core SPIR-V version must not be directly enabled by *both* and extension and a capability. There are 78 existing cases that break this rule, so grandparent them in with an allow-list. * Add "version": "None" to enums added for a recent extension Add it for the HostAccessQualifier enums from SPV_INTEL_global_variable_host_access
2023-08-16Headers support for two Intel extensions (#356)Viktoria Maximova10-0/+257
* Add SPV_INTEL_global_variable_fpga_decorations Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_global_variable_fpga_decorations.asciidoc * Add SPV_INTEL_global_variable_host_access Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_global_variable_host_access.asciidoc * Update headers generator * update headers after generating script
2023-08-10Merge pull request #366 from KonstantinSeurer/mainBen Ashbaugh10-0/+307
Add SPV_AMDX_shader_enqueue
2023-08-10Revert "Merge pull request #367 from dneto0/coop-matrix-enums-deps"David Neto1-11/+0
This reverts commit 124a9665e464ef98b8b718d572d5f329311061eb, reversing changes made to f14a663c84e8da4776bd615ac19450aa4d03cd71.
2023-08-04Cooperative matrix enums depend on the extensionDavid Neto1-0/+11
This fixes basic parsing in SPIRV-Tools. An enum is considered invisible by SPIRV-Tools if: - it is not in any SPIR-V core version - it has no enabling capabilities - it has no enabling extensions So make the new cooperative matrix enums depend on the extension, since they are not in any core version of SPIR-V, and don't depend on any capabilities.
2023-08-04Add SPV_AMDX_shader_enqueueKonstantin Seurer10-0/+307
2023-08-02Merge pull request #361 from kpet/coop-matrix-capabilities-alignmentJohn Kessenich1-11/+0
Remove capabilities on cooperative matrix enums to align with specifcation
2023-07-26Add KHR suffix to Cooperative Matrix OperandsKevin Petit10-91/+91
Signed-off-by: Kevin Petit <kevin.petit@arm.com> Change-Id: I0303c1b16e46e77f0e7e95999c606cc75f7f0d4c
2023-07-21Recommit PR #348 - Add fp-max-error support (#363)asudarsa10-0/+33
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
2023-07-19Revert "Add support for fp_max_error extension"alan-baker10-33/+0
2023-07-19Remove capabilities on cooperative matrix enums to align with specificationKevin Petit1-11/+0
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
2023-07-19Merge pull request #348 from asudarsa/asudarsa/add_fp_max_error_supportBen Ashbaugh10-0/+33
Add support for fp_max_error extension
2023-07-06Add WGSL source languageAlan Baker10-1/+14
See https://www.w3.org/TR/WGSL/
2023-07-05Regenerate headersSirLynix1-1/+1
2023-06-30Add NZSL as a source languageJérôme Leclercq10-1/+14
2023-06-21fix operand namesKevin Petit1-4/+4
2023-06-21Change kind of FPMaxErrorDecorationINTEL to LiteralFloatArvind Sudarsanam1-1/+1
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
2023-06-21Add definitions for SPV_KHR_cooperative_matrixKevin Petit10-0/+514
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
2023-06-21Add definitions for SVP_EXT_image_raw10_raw12Kevin Petit10-1/+29
2023-06-09Interchange capability and decorationArvind Sudarsanam10-21/+21
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
2023-06-09Merge remote-tracking branch 'real-origin/main' into ↵Arvind Sudarsanam10-48/+331
asudarsa/add_fp_max_error_support
2023-05-31Merge branch 'main' of https://github.com/KhronosGroup/SPIRV-HeadersHenry Rose10-40/+118
2023-05-31regenerate headers & correct order of TileImage*ReadAccessEXT Capability enumHenry Rose10-19/+39
2023-05-31add HERO_C to the source language enumerationHenry Rose1-1/+1
2023-05-17Make the generated operators for masks constexprKevin Petit1-40/+40
Generate the overloaded C++11 operators as constexpr instead of inline. constexpr implies inline but makes it possible to use the operators in constexpr functions. Signed-off-by: Kevin Petit <kevin.petit@arm.com>
2023-04-26SPV_KHR_ray_tracing_position_fetchEric Werness10-0/+78
2023-04-19Fix TileImage capabilities orderSidorov, Dmitry2-18/+29
I'm getting: Error: "Capability" enumerant "TileImageColorReadAccessEXT" is out of order. It has value 4166 but follows the enumerant with value 4450 without this patch. Also the script generated .bf file Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
2023-04-13Add Hero C Compiler to the vendor list & add C source language to the Source ↵Henry Rose1-0/+4
Language enum
2023-04-05Add back version field for new enumerants and operands, but set to None.Jan-Harald Fredriksen1-11/+22
2023-04-05Address feedback on incorrect use of version and extension fields.Jan-Harald Fredriksen1-30/+10
2023-04-04Add SPV_EXT_shader_tile_image.Jan-Harald Fredriksen9-1/+192
2023-03-17Simplify enabling capabilities for image DimGraeme Leese1-6/+5
A lot of these capabilities implied another of the enabling capabilities so didn't really serve their intended purpose. Remove them to simplify this section of the grammar. This affects one table in the spec and a corresponding spec change will clarify that this makes no change to the meaning or scope of these capabilities.
2023-03-09Add parametersArvind Sudarsanam1-0/+3
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
2023-03-08Merge remote-tracking branch 'real-origin/main' into ↵Arvind Sudarsanam10-0/+333
asudarsa/add_fp_max_error_support
2023-03-09Merge pull request #320 from CodeLinaro/spv-qcom-image-processingJohn Kessenich10-0/+183
SPV_QCOM_image_processing, fixes #307
2023-03-09Merge pull request #321 from asudarsa/asudarsa/add_fpga_latency_control_extJohn Kessenich10-0/+53
Add support for FPGA latency control extension
2023-03-08Fix error in merge conflict resolutionArvind Sudarsanam1-1/+0
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
2023-03-07Merge remote-tracking branch 'real-origin/main' into ↵Arvind Sudarsanam10-0/+35
asudarsa/add_fpga_latency_control_ext
2023-03-06headers support for SPV_INTEL_bfloat16_conversionBen Ashbaugh10-0/+63
2023-03-03Add parametersArvind Sudarsanam1-0/+8
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
2023-03-03Remove redundant extensions entryArvind Sudarsanam1-2/+0
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
2023-03-02Add support for SPV_INTEL_fpga_latency_control extensionArvind Sudarsanam10-0/+47
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
2023-03-01SPV_QCOM_image_processingWooyoung Kim1-1/+0
2023-03-01SPV_QCOM_image_processingWooyoung Kim1-3/+3
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