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-rw-r--r--include/spirv/unified1/spirv.bf20
-rw-r--r--include/spirv/unified1/spirv.core.grammar.json92
-rw-r--r--include/spirv/unified1/spirv.cs20
-rw-r--r--include/spirv/unified1/spirv.h20
-rw-r--r--include/spirv/unified1/spirv.hpp20
-rw-r--r--include/spirv/unified1/spirv.hpp1120
-rw-r--r--include/spirv/unified1/spirv.json30
-rw-r--r--include/spirv/unified1/spirv.lua18
-rw-r--r--include/spirv/unified1/spirv.py18
-rw-r--r--include/spirv/unified1/spv.d20
-rw-r--r--tools/buildHeaders/jsonToSpirv.cpp10
-rw-r--r--tools/buildHeaders/jsonToSpirv.h2
12 files changed, 288 insertions, 2 deletions
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
index 807a7c5..7326fbf 100644
--- a/include/spirv/unified1/spirv.bf
+++ b/include/spirv/unified1/spirv.bf
@@ -614,6 +614,8 @@ namespace Spv
MMHostInterfaceMaxBurstINTEL = 6181,
MMHostInterfaceWaitRequestINTEL = 6182,
StableKernelArgumentINTEL = 6183,
+ CacheControlLoadINTEL = 6442,
+ CacheControlStoreINTEL = 6443,
}
[AllowDuplicates, CRepr] public enum BuiltIn
@@ -1198,6 +1200,7 @@ namespace Spv
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
+ CacheControlsINTEL = 6441,
}
[AllowDuplicates, CRepr] public enum RayFlagsShift
@@ -1351,6 +1354,23 @@ namespace Spv
ReadWriteINTEL = 3,
}
+ [AllowDuplicates, CRepr] public enum LoadCacheControl
+ {
+ UncachedINTEL = 0,
+ CachedINTEL = 1,
+ StreamingINTEL = 2,
+ InvalidateAfterReadINTEL = 3,
+ ConstCachedINTEL = 4,
+ }
+
+ [AllowDuplicates, CRepr] public enum StoreCacheControl
+ {
+ UncachedINTEL = 0,
+ WriteThroughINTEL = 1,
+ WriteBackINTEL = 2,
+ StreamingINTEL = 3,
+ }
+
[AllowDuplicates, CRepr] public enum Op
{
OpNop = 0,
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index b6bbc2c..e9d4b3e 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -13642,6 +13642,26 @@
"value" : 6183,
"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
"version" : "None"
+ },
+ {
+ "enumerant" : "CacheControlLoadINTEL",
+ "value" : 6442,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Cache Level'" },
+ { "kind" : "LoadCacheControl", "name" : "'Cache Control'" }
+ ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "CacheControlStoreINTEL",
+ "value" : 6443,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Cache Level'" },
+ { "kind" : "StoreCacheControl", "name" : "'Cache Control'" }
+ ],
+ "version" : "None"
}
]
},
@@ -16190,6 +16210,12 @@
"value" : 6400,
"extensions" : [ "SPV_KHR_uniform_group_instructions"],
"version" : "None"
+ },
+ {
+ "enumerant" : "CacheControlsINTEL",
+ "value" : 6441,
+ "extensions" : [ "SPV_INTEL_cache_controls" ],
+ "version" : "None"
}
]
},
@@ -16362,6 +16388,72 @@
]
},
{
+ "category" : "ValueEnum",
+ "kind" : "LoadCacheControl",
+ "enumerants" : [
+ {
+ "enumerant" : "UncachedINTEL",
+ "value" : 0,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "CachedINTEL",
+ "value" : 1,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "StreamingINTEL",
+ "value" : 2,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "InvalidateAfterReadINTEL",
+ "value" : 3,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "ConstCachedINTEL",
+ "value" : 4,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ }
+ ]
+ },
+ {
+ "category" : "ValueEnum",
+ "kind" : "StoreCacheControl",
+ "enumerants" : [
+ {
+ "enumerant" : "UncachedINTEL",
+ "value" : 0,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "WriteThroughINTEL",
+ "value" : 1,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "WriteBackINTEL",
+ "value" : 2,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "StreamingINTEL",
+ "value" : 3,
+ "capabilities" : [ "CacheControlsINTEL" ],
+ "version" : "None"
+ }
+ ]
+ },
+ {
"category" : "Id",
"kind" : "IdResultType",
"doc" : "Reference to an <id> representing the result's type of the enclosing instruction"
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 79369a8..ccf020e 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -613,6 +613,8 @@ namespace Spv
MMHostInterfaceMaxBurstINTEL = 6181,
MMHostInterfaceWaitRequestINTEL = 6182,
StableKernelArgumentINTEL = 6183,
+ CacheControlLoadINTEL = 6442,
+ CacheControlStoreINTEL = 6443,
}
public enum BuiltIn
@@ -1197,6 +1199,7 @@ namespace Spv
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
+ CacheControlsINTEL = 6441,
}
public enum RayFlagsShift
@@ -1350,6 +1353,23 @@ namespace Spv
ReadWriteINTEL = 3,
}
+ public enum LoadCacheControl
+ {
+ UncachedINTEL = 0,
+ CachedINTEL = 1,
+ StreamingINTEL = 2,
+ InvalidateAfterReadINTEL = 3,
+ ConstCachedINTEL = 4,
+ }
+
+ public enum StoreCacheControl
+ {
+ UncachedINTEL = 0,
+ WriteThroughINTEL = 1,
+ WriteBackINTEL = 2,
+ StreamingINTEL = 3,
+ }
+
public enum Op
{
OpNop = 0,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index d381340..c96987b 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -619,6 +619,8 @@ typedef enum SpvDecoration_ {
SpvDecorationMMHostInterfaceMaxBurstINTEL = 6181,
SpvDecorationMMHostInterfaceWaitRequestINTEL = 6182,
SpvDecorationStableKernelArgumentINTEL = 6183,
+ SpvDecorationCacheControlLoadINTEL = 6442,
+ SpvDecorationCacheControlStoreINTEL = 6443,
SpvDecorationMax = 0x7fffffff,
} SpvDecoration;
@@ -1197,6 +1199,7 @@ typedef enum SpvCapability_ {
SpvCapabilityFPGALatencyControlINTEL = 6171,
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
+ SpvCapabilityCacheControlsINTEL = 6441,
SpvCapabilityMax = 0x7fffffff,
} SpvCapability;
@@ -1348,6 +1351,23 @@ typedef enum SpvHostAccessQualifier_ {
SpvHostAccessQualifierMax = 0x7fffffff,
} SpvHostAccessQualifier;
+typedef enum SpvLoadCacheControl_ {
+ SpvLoadCacheControlUncachedINTEL = 0,
+ SpvLoadCacheControlCachedINTEL = 1,
+ SpvLoadCacheControlStreamingINTEL = 2,
+ SpvLoadCacheControlInvalidateAfterReadINTEL = 3,
+ SpvLoadCacheControlConstCachedINTEL = 4,
+ SpvLoadCacheControlMax = 0x7fffffff,
+} SpvLoadCacheControl;
+
+typedef enum SpvStoreCacheControl_ {
+ SpvStoreCacheControlUncachedINTEL = 0,
+ SpvStoreCacheControlWriteThroughINTEL = 1,
+ SpvStoreCacheControlWriteBackINTEL = 2,
+ SpvStoreCacheControlStreamingINTEL = 3,
+ SpvStoreCacheControlMax = 0x7fffffff,
+} SpvStoreCacheControl;
+
typedef enum SpvOp_ {
SpvOpNop = 0,
SpvOpUndef = 1,
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index b9a881f..ddade40 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -615,6 +615,8 @@ enum Decoration {
DecorationMMHostInterfaceMaxBurstINTEL = 6181,
DecorationMMHostInterfaceWaitRequestINTEL = 6182,
DecorationStableKernelArgumentINTEL = 6183,
+ DecorationCacheControlLoadINTEL = 6442,
+ DecorationCacheControlStoreINTEL = 6443,
DecorationMax = 0x7fffffff,
};
@@ -1193,6 +1195,7 @@ enum Capability {
CapabilityFPGALatencyControlINTEL = 6171,
CapabilityFPGAArgumentInterfacesINTEL = 6174,
CapabilityGroupUniformArithmeticKHR = 6400,
+ CapabilityCacheControlsINTEL = 6441,
CapabilityMax = 0x7fffffff,
};
@@ -1344,6 +1347,23 @@ enum HostAccessQualifier {
HostAccessQualifierMax = 0x7fffffff,
};
+enum LoadCacheControl {
+ LoadCacheControlUncachedINTEL = 0,
+ LoadCacheControlCachedINTEL = 1,
+ LoadCacheControlStreamingINTEL = 2,
+ LoadCacheControlInvalidateAfterReadINTEL = 3,
+ LoadCacheControlConstCachedINTEL = 4,
+ LoadCacheControlMax = 0x7fffffff,
+};
+
+enum StoreCacheControl {
+ StoreCacheControlUncachedINTEL = 0,
+ StoreCacheControlWriteThroughINTEL = 1,
+ StoreCacheControlWriteBackINTEL = 2,
+ StoreCacheControlStreamingINTEL = 3,
+ StoreCacheControlMax = 0x7fffffff,
+};
+
enum Op {
OpNop = 0,
OpUndef = 1,
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index f7c3e23..b627d95 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -615,6 +615,8 @@ enum class Decoration : unsigned {
MMHostInterfaceMaxBurstINTEL = 6181,
MMHostInterfaceWaitRequestINTEL = 6182,
StableKernelArgumentINTEL = 6183,
+ CacheControlLoadINTEL = 6442,
+ CacheControlStoreINTEL = 6443,
Max = 0x7fffffff,
};
@@ -1193,6 +1195,7 @@ enum class Capability : unsigned {
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
+ CacheControlsINTEL = 6441,
Max = 0x7fffffff,
};
@@ -1344,6 +1347,23 @@ enum class HostAccessQualifier : unsigned {
Max = 0x7fffffff,
};
+enum class LoadCacheControl : unsigned {
+ UncachedINTEL = 0,
+ CachedINTEL = 1,
+ StreamingINTEL = 2,
+ InvalidateAfterReadINTEL = 3,
+ ConstCachedINTEL = 4,
+ Max = 0x7fffffff,
+};
+
+enum class StoreCacheControl : unsigned {
+ UncachedINTEL = 0,
+ WriteThroughINTEL = 1,
+ WriteBackINTEL = 2,
+ StreamingINTEL = 3,
+ Max = 0x7fffffff,
+};
+
enum class Op : unsigned {
OpNop = 0,
OpUndef = 1,
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index b1b60a4..c130939 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -640,7 +640,9 @@
"MMHostInterfaceReadWriteModeINTEL": 6180,
"MMHostInterfaceMaxBurstINTEL": 6181,
"MMHostInterfaceWaitRequestINTEL": 6182,
- "StableKernelArgumentINTEL": 6183
+ "StableKernelArgumentINTEL": 6183,
+ "CacheControlLoadINTEL": 6442,
+ "CacheControlStoreINTEL": 6443
}
},
{
@@ -1172,7 +1174,8 @@
"FPMaxErrorINTEL": 6169,
"FPGALatencyControlINTEL": 6171,
"FPGAArgumentInterfacesINTEL": 6174,
- "GroupUniformArithmeticKHR": 6400
+ "GroupUniformArithmeticKHR": 6400,
+ "CacheControlsINTEL": 6441
}
},
{
@@ -1337,6 +1340,29 @@
}
},
{
+ "Name": "LoadCacheControl",
+ "Type": "Value",
+ "Values":
+ {
+ "UncachedINTEL": 0,
+ "CachedINTEL": 1,
+ "StreamingINTEL": 2,
+ "InvalidateAfterReadINTEL": 3,
+ "ConstCachedINTEL": 4
+ }
+ },
+ {
+ "Name": "StoreCacheControl",
+ "Type": "Value",
+ "Values":
+ {
+ "UncachedINTEL": 0,
+ "WriteThroughINTEL": 1,
+ "WriteBackINTEL": 2,
+ "StreamingINTEL": 3
+ }
+ },
+ {
"Name": "Op",
"Type": "Value",
"Values":
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index 893b901..49d790b 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -588,6 +588,8 @@ spv = {
MMHostInterfaceMaxBurstINTEL = 6181,
MMHostInterfaceWaitRequestINTEL = 6182,
StableKernelArgumentINTEL = 6183,
+ CacheControlLoadINTEL = 6442,
+ CacheControlStoreINTEL = 6443,
},
BuiltIn = {
@@ -1155,6 +1157,7 @@ spv = {
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
+ CacheControlsINTEL = 6441,
},
RayFlagsShift = {
@@ -1290,6 +1293,21 @@ spv = {
ReadWriteINTEL = 3,
},
+ LoadCacheControl = {
+ UncachedINTEL = 0,
+ CachedINTEL = 1,
+ StreamingINTEL = 2,
+ InvalidateAfterReadINTEL = 3,
+ ConstCachedINTEL = 4,
+ },
+
+ StoreCacheControl = {
+ UncachedINTEL = 0,
+ WriteThroughINTEL = 1,
+ WriteBackINTEL = 2,
+ StreamingINTEL = 3,
+ },
+
Op = {
OpNop = 0,
OpUndef = 1,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index 83bba7b..7dedc21 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -588,6 +588,8 @@ spv = {
'MMHostInterfaceMaxBurstINTEL' : 6181,
'MMHostInterfaceWaitRequestINTEL' : 6182,
'StableKernelArgumentINTEL' : 6183,
+ 'CacheControlLoadINTEL' : 6442,
+ 'CacheControlStoreINTEL' : 6443,
},
'BuiltIn' : {
@@ -1155,6 +1157,7 @@ spv = {
'FPGALatencyControlINTEL' : 6171,
'FPGAArgumentInterfacesINTEL' : 6174,
'GroupUniformArithmeticKHR' : 6400,
+ 'CacheControlsINTEL' : 6441,
},
'RayFlagsShift' : {
@@ -1290,6 +1293,21 @@ spv = {
'ReadWriteINTEL' : 3,
},
+ 'LoadCacheControl' : {
+ 'UncachedINTEL' : 0,
+ 'CachedINTEL' : 1,
+ 'StreamingINTEL' : 2,
+ 'InvalidateAfterReadINTEL' : 3,
+ 'ConstCachedINTEL' : 4,
+ },
+
+ 'StoreCacheControl' : {
+ 'UncachedINTEL' : 0,
+ 'WriteThroughINTEL' : 1,
+ 'WriteBackINTEL' : 2,
+ 'StreamingINTEL' : 3,
+ },
+
'Op' : {
'OpNop' : 0,
'OpUndef' : 1,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index dc3bbfb..1f79ee3 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -616,6 +616,8 @@ enum Decoration : uint
MMHostInterfaceMaxBurstINTEL = 6181,
MMHostInterfaceWaitRequestINTEL = 6182,
StableKernelArgumentINTEL = 6183,
+ CacheControlLoadINTEL = 6442,
+ CacheControlStoreINTEL = 6443,
}
enum BuiltIn : uint
@@ -1200,6 +1202,7 @@ enum Capability : uint
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
+ CacheControlsINTEL = 6441,
}
enum RayFlagsShift : uint
@@ -1353,6 +1356,23 @@ enum HostAccessQualifier : uint
ReadWriteINTEL = 3,
}
+enum LoadCacheControl : uint
+{
+ UncachedINTEL = 0,
+ CachedINTEL = 1,
+ StreamingINTEL = 2,
+ InvalidateAfterReadINTEL = 3,
+ ConstCachedINTEL = 4,
+}
+
+enum StoreCacheControl : uint
+{
+ UncachedINTEL = 0,
+ WriteThroughINTEL = 1,
+ WriteBackINTEL = 2,
+ StreamingINTEL = 3,
+}
+
enum Op : uint
{
OpNop = 0,
diff --git a/tools/buildHeaders/jsonToSpirv.cpp b/tools/buildHeaders/jsonToSpirv.cpp
index 6135cd9..04f8079 100644
--- a/tools/buildHeaders/jsonToSpirv.cpp
+++ b/tools/buildHeaders/jsonToSpirv.cpp
@@ -270,6 +270,8 @@ EnumValues CooperativeMatrixLayoutParams;
EnumValues CooperativeMatrixUseParams;
EnumValues InitializationModeQualifierParams;
EnumValues HostAccessQualifierParams;
+EnumValues LoadCacheControlParams;
+EnumValues StoreCacheControlParams;
std::pair<bool, std::string> ReadFile(const std::string& path)
{
@@ -428,6 +430,10 @@ ClassOptionality ToOperandClassAndOptionality(const std::string& operandKind, co
type = OperandInitializationModeQualifier;
} else if (operandKind == "HostAccessQualifier") {
type = OperandHostAccessQualifier;
+ } else if (operandKind == "LoadCacheControl") {
+ type = OperandLoadCacheControl;
+ } else if (operandKind == "StoreCacheControl") {
+ type = OperandStoreCacheControl;
}
if (type == OperandNone) {
@@ -763,6 +769,10 @@ void jsonToSpirv(const std::string& jsonPath, bool buildingHeaders)
establishOperandClass(enumName, OperandInitializationModeQualifier, &InitializationModeQualifierParams, operandEnum, category);
} else if (enumName == "HostAccessQualifier") {
establishOperandClass(enumName, OperandHostAccessQualifier, &HostAccessQualifierParams, operandEnum, category);
+ } else if (enumName == "LoadCacheControl") {
+ establishOperandClass(enumName, OperandLoadCacheControl, &LoadCacheControlParams, operandEnum, category);
+ } else if (enumName == "StoreCacheControl") {
+ establishOperandClass(enumName, OperandStoreCacheControl, &StoreCacheControlParams, operandEnum, category);
}
}
diff --git a/tools/buildHeaders/jsonToSpirv.h b/tools/buildHeaders/jsonToSpirv.h
index 5e96218..db4855b 100644
--- a/tools/buildHeaders/jsonToSpirv.h
+++ b/tools/buildHeaders/jsonToSpirv.h
@@ -101,6 +101,8 @@ enum OperandClass {
OperandCooperativeMatrixUse,
OperandInitializationModeQualifier,
OperandHostAccessQualifier,
+ OperandLoadCacheControl,
+ OperandStoreCacheControl,
OperandOpcode,
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 00:25:32 +0000