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-rw-r--r--include/spirv/unified1/spirv.bf17
-rw-r--r--include/spirv/unified1/spirv.core.grammar.json162
-rw-r--r--include/spirv/unified1/spirv.cs17
-rw-r--r--include/spirv/unified1/spirv.h23
-rw-r--r--include/spirv/unified1/spirv.hpp23
-rw-r--r--include/spirv/unified1/spirv.hpp1123
-rw-r--r--include/spirv/unified1/spirv.json17
-rw-r--r--include/spirv/unified1/spirv.lua17
-rw-r--r--include/spirv/unified1/spirv.py17
-rw-r--r--include/spirv/unified1/spv.d17
10 files changed, 333 insertions, 0 deletions
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
index 19ddb95..5380651 100644
--- a/include/spirv/unified1/spirv.bf
+++ b/include/spirv/unified1/spirv.bf
@@ -193,6 +193,7 @@ namespace Spv
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
StreamingInterfaceINTEL = 6154,
+ RegisterMapInterfaceINTEL = 6160,
NamedBarrierCountINTEL = 6417,
}
@@ -507,6 +508,8 @@ namespace Spv
MaxByteOffsetId = 47,
NoSignedWrap = 4469,
NoUnsignedWrap = 4470,
+ WeightTextureQCOM = 4487,
+ BlockMatchTextureQCOM = 4488,
ExplicitInterpAMD = 4999,
OverrideCoverageNV = 5248,
PassthroughNV = 5250,
@@ -576,6 +579,8 @@ namespace Spv
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
FPMaxErrorINTEL = 6170,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1020,6 +1025,9 @@ namespace Spv
RayQueryKHR = 4472,
RayTraversalPrimitiveCullingKHR = 4478,
RayTracingKHR = 4479,
+ TextureSampleWeightedQCOM = 4484,
+ TextureBoxFilterQCOM = 4485,
+ TextureBlockMatchQCOM = 4486,
Float16ImageAMD = 5008,
ImageGatherBiasLodAMD = 5009,
FragmentMaskAMD = 5010,
@@ -1147,8 +1155,11 @@ namespace Spv
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
+ FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorDecorationINTEL = 6169,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
@@ -1636,6 +1647,10 @@ namespace Spv
OpRayQueryConfirmIntersectionKHR = 4476,
OpRayQueryProceedKHR = 4477,
OpRayQueryGetIntersectionTypeKHR = 4479,
+ OpImageSampleWeightedQCOM = 4480,
+ OpImageBoxFilterQCOM = 4481,
+ OpImageBlockMatchSSDQCOM = 4482,
+ OpImageBlockMatchSADQCOM = 4483,
OpGroupIAddNonUniformAMD = 5000,
OpGroupFAddNonUniformAMD = 5001,
OpGroupFMinNonUniformAMD = 5002,
@@ -1953,6 +1968,8 @@ namespace Spv
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index a916fd7..ad0d2ca 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -4593,6 +4593,66 @@
"version" : "None"
},
{
+ "opname" : "OpImageSampleWeightedQCOM",
+ "class" : "Image",
+ "opcode" : 4480,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Texture'" },
+ { "kind" : "IdRef", "name" : "'Coordinates'" },
+ { "kind" : "IdRef", "name" : "'Weights'" }
+ ],
+ "capabilities" : [ "TextureSampleWeightedQCOM" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpImageBoxFilterQCOM",
+ "class" : "Image",
+ "opcode" : 4481,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Texture'" },
+ { "kind" : "IdRef", "name" : "'Coordinates'" },
+ { "kind" : "IdRef", "name" : "'Box Size'" }
+ ],
+ "capabilities" : [ "TextureBoxFilterQCOM" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpImageBlockMatchSSDQCOM",
+ "class" : "Image",
+ "opcode" : 4482,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Target'" },
+ { "kind" : "IdRef", "name" : "'Target Coordinates'" },
+ { "kind" : "IdRef", "name" : "'Reference'" },
+ { "kind" : "IdRef", "name" : "'Reference Coordinates'" },
+ { "kind" : "IdRef", "name" : "'Block Size'" }
+ ],
+ "capabilities" : [ "TextureBlockMatchQCOM" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpImageBlockMatchSADQCOM",
+ "class" : "Image",
+ "opcode" : 4483,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Target'" },
+ { "kind" : "IdRef", "name" : "'Target Coordinates'" },
+ { "kind" : "IdRef", "name" : "'Reference'" },
+ { "kind" : "IdRef", "name" : "'Reference Coordinates'" },
+ { "kind" : "IdRef", "name" : "'Block Size'" }
+ ],
+ "capabilities" : [ "TextureBlockMatchQCOM" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpGroupIAddNonUniformAMD",
"class" : "Group",
"opcode" : 5000,
@@ -9044,6 +9104,30 @@
"version" : "None"
},
{
+ "opname" : "OpConvertFToBF16INTEL",
+ "class" : "Conversion",
+ "opcode" : 6116,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Float Value'" }
+ ],
+ "capabilities" : [ "BFloat16ConversionINTEL" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpConvertBF16ToFINTEL",
+ "class" : "Conversion",
+ "opcode" : 6117,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'BFloat16 Value'" }
+ ],
+ "capabilities" : [ "BFloat16ConversionINTEL" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpControlBarrierArriveINTEL",
"class" : "Barrier",
"opcode" : 6142,
@@ -10716,6 +10800,15 @@
"version" : "None"
},
{
+ "enumerant" : "RegisterMapInterfaceINTEL",
+ "value" : 6160,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'WaitForDoneWrite'" }
+ ],
+ "capabilities" : [ "FPGAKernelAttributesv2INTEL" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "NamedBarrierCountINTEL",
"value" : 6417,
"parameters" : [
@@ -11987,6 +12080,18 @@
"version" : "1.4"
},
{
+ "enumerant" : "WeightTextureQCOM",
+ "value" : 4487,
+ "extensions" : [ "SPV_QCOM_image_processing" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "BlockMatchTextureQCOM",
+ "value" : 4488,
+ "extensions" : [ "SPV_QCOM_image_processing" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "ExplicitInterpAMD",
"value" : 4999,
"extensions" : [ "SPV_AMD_shader_explicit_vertex_parameter" ],
@@ -12524,6 +12629,26 @@
"version" : "None"
},
{
+ "enumerant" : "LatencyControlLabelINTEL",
+ "value" : 6172,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Latency Label'" }
+ ],
+ "capabilities" : [ "FPGALatencyControlINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "LatencyControlConstraintINTEL",
+ "value" : 6173,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Relative To'" },
+ { "kind" : "LiteralInteger", "name" : "'Control Type'" },
+ { "kind" : "LiteralInteger", "name" : "'Relative Cycle'" }
+ ],
+ "capabilities" : [ "FPGALatencyControlINTEL" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "ConduitKernelArgumentINTEL",
"value" : 6175,
"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
@@ -14089,6 +14214,24 @@
"version" : "None"
},
{
+ "enumerant" : "TextureSampleWeightedQCOM",
+ "value" : 4484,
+ "extensions" : [ "SPV_QCOM_image_processing" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "TextureBoxFilterQCOM",
+ "value" : 4485,
+ "extensions" : [ "SPV_QCOM_image_processing" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "TextureBlockMatchQCOM",
+ "value" : 4486,
+ "extensions" : [ "SPV_QCOM_image_processing" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "Float16ImageAMD",
"value" : 5008,
"capabilities" : [ "Shader" ],
@@ -14894,18 +15037,37 @@
"version" : "None"
},
{
+ "enumerant" : "BFloat16ConversionINTEL",
+ "value" : 6115,
+ "extensions" : [ "SPV_INTEL_bfloat16_conversion" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "SplitBarrierINTEL",
"value" : 6141,
"extensions" : [ "SPV_INTEL_split_barrier" ],
"version" : "None"
},
{
+ "enumerant" : "FPGAKernelAttributesv2INTEL",
+ "value" : 6161,
+ "capabilities" : [ "FPGAKernelAttributesINTEL" ],
+ "extensions" : [ "SPV_INTEL_kernel_attributes" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "FPMaxErrorDecorationINTEL",
"value" : 6169,
"extensions" : [ "SPV_INTEL_fp_max_error" ],
"version" : "None"
},
{
+ "enumerant" : "FPGALatencyControlINTEL",
+ "value" : 6171,
+ "extensions" : [ "SPV_INTEL_fpga_latency_control" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "FPGAArgumentInterfacesINTEL",
"value" : 6174,
"extensions" : [ "SPV_INTEL_fpga_argument_interfaces" ],
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 28f8151..ae3840e 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -192,6 +192,7 @@ namespace Spv
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
StreamingInterfaceINTEL = 6154,
+ RegisterMapInterfaceINTEL = 6160,
NamedBarrierCountINTEL = 6417,
}
@@ -506,6 +507,8 @@ namespace Spv
MaxByteOffsetId = 47,
NoSignedWrap = 4469,
NoUnsignedWrap = 4470,
+ WeightTextureQCOM = 4487,
+ BlockMatchTextureQCOM = 4488,
ExplicitInterpAMD = 4999,
OverrideCoverageNV = 5248,
PassthroughNV = 5250,
@@ -575,6 +578,8 @@ namespace Spv
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
FPMaxErrorINTEL = 6170,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1019,6 +1024,9 @@ namespace Spv
RayQueryKHR = 4472,
RayTraversalPrimitiveCullingKHR = 4478,
RayTracingKHR = 4479,
+ TextureSampleWeightedQCOM = 4484,
+ TextureBoxFilterQCOM = 4485,
+ TextureBlockMatchQCOM = 4486,
Float16ImageAMD = 5008,
ImageGatherBiasLodAMD = 5009,
FragmentMaskAMD = 5010,
@@ -1146,8 +1154,11 @@ namespace Spv
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
+ FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorDecorationINTEL = 6169,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
@@ -1635,6 +1646,10 @@ namespace Spv
OpRayQueryConfirmIntersectionKHR = 4476,
OpRayQueryProceedKHR = 4477,
OpRayQueryGetIntersectionTypeKHR = 4479,
+ OpImageSampleWeightedQCOM = 4480,
+ OpImageBoxFilterQCOM = 4481,
+ OpImageBlockMatchSSDQCOM = 4482,
+ OpImageBlockMatchSADQCOM = 4483,
OpGroupIAddNonUniformAMD = 5000,
OpGroupFAddNonUniformAMD = 5001,
OpGroupFMinNonUniformAMD = 5002,
@@ -1952,6 +1967,8 @@ namespace Spv
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index bb0fa79..e9ba5fb 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -200,6 +200,7 @@ typedef enum SpvExecutionMode_ {
SpvExecutionModeNumSIMDWorkitemsINTEL = 5896,
SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
SpvExecutionModeStreamingInterfaceINTEL = 6154,
+ SpvExecutionModeRegisterMapInterfaceINTEL = 6160,
SpvExecutionModeNamedBarrierCountINTEL = 6417,
SpvExecutionModeMax = 0x7fffffff,
} SpvExecutionMode;
@@ -512,6 +513,8 @@ typedef enum SpvDecoration_ {
SpvDecorationMaxByteOffsetId = 47,
SpvDecorationNoSignedWrap = 4469,
SpvDecorationNoUnsignedWrap = 4470,
+ SpvDecorationWeightTextureQCOM = 4487,
+ SpvDecorationBlockMatchTextureQCOM = 4488,
SpvDecorationExplicitInterpAMD = 4999,
SpvDecorationOverrideCoverageNV = 5248,
SpvDecorationPassthroughNV = 5250,
@@ -581,6 +584,8 @@ typedef enum SpvDecoration_ {
SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
SpvDecorationMediaBlockIOINTEL = 6140,
SpvDecorationFPMaxErrorINTEL = 6170,
+ SpvDecorationLatencyControlLabelINTEL = 6172,
+ SpvDecorationLatencyControlConstraintINTEL = 6173,
SpvDecorationConduitKernelArgumentINTEL = 6175,
SpvDecorationRegisterMapKernelArgumentINTEL = 6176,
SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1019,6 +1024,9 @@ typedef enum SpvCapability_ {
SpvCapabilityRayQueryKHR = 4472,
SpvCapabilityRayTraversalPrimitiveCullingKHR = 4478,
SpvCapabilityRayTracingKHR = 4479,
+ SpvCapabilityTextureSampleWeightedQCOM = 4484,
+ SpvCapabilityTextureBoxFilterQCOM = 4485,
+ SpvCapabilityTextureBlockMatchQCOM = 4486,
SpvCapabilityFloat16ImageAMD = 5008,
SpvCapabilityImageGatherBiasLodAMD = 5009,
SpvCapabilityFragmentMaskAMD = 5010,
@@ -1146,8 +1154,11 @@ typedef enum SpvCapability_ {
SpvCapabilityOptNoneINTEL = 6094,
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
+ SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierINTEL = 6141,
+ SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
SpvCapabilityFPMaxErrorDecorationINTEL = 6169,
+ SpvCapabilityFPGALatencyControlINTEL = 6171,
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMax = 0x7fffffff,
@@ -1633,6 +1644,10 @@ typedef enum SpvOp_ {
SpvOpRayQueryConfirmIntersectionKHR = 4476,
SpvOpRayQueryProceedKHR = 4477,
SpvOpRayQueryGetIntersectionTypeKHR = 4479,
+ SpvOpImageSampleWeightedQCOM = 4480,
+ SpvOpImageBoxFilterQCOM = 4481,
+ SpvOpImageBlockMatchSSDQCOM = 4482,
+ SpvOpImageBlockMatchSADQCOM = 4483,
SpvOpGroupIAddNonUniformAMD = 5000,
SpvOpGroupFAddNonUniformAMD = 5001,
SpvOpGroupFMinNonUniformAMD = 5002,
@@ -1950,6 +1965,8 @@ typedef enum SpvOp_ {
SpvOpTypeStructContinuedINTEL = 6090,
SpvOpConstantCompositeContinuedINTEL = 6091,
SpvOpSpecConstantCompositeContinuedINTEL = 6092,
+ SpvOpConvertFToBF16INTEL = 6116,
+ SpvOpConvertBF16ToFINTEL = 6117,
SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpGroupIMulKHR = 6401,
@@ -2341,6 +2358,10 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break;
case SpvOpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpImageSampleWeightedQCOM: *hasResult = true; *hasResultType = true; break;
+ case SpvOpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break;
+ case SpvOpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break;
+ case SpvOpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
@@ -2653,6 +2674,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index 013bd61..8b12b0e 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -196,6 +196,7 @@ enum ExecutionMode {
ExecutionModeNumSIMDWorkitemsINTEL = 5896,
ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
ExecutionModeStreamingInterfaceINTEL = 6154,
+ ExecutionModeRegisterMapInterfaceINTEL = 6160,
ExecutionModeNamedBarrierCountINTEL = 6417,
ExecutionModeMax = 0x7fffffff,
};
@@ -508,6 +509,8 @@ enum Decoration {
DecorationMaxByteOffsetId = 47,
DecorationNoSignedWrap = 4469,
DecorationNoUnsignedWrap = 4470,
+ DecorationWeightTextureQCOM = 4487,
+ DecorationBlockMatchTextureQCOM = 4488,
DecorationExplicitInterpAMD = 4999,
DecorationOverrideCoverageNV = 5248,
DecorationPassthroughNV = 5250,
@@ -577,6 +580,8 @@ enum Decoration {
DecorationVectorComputeCallableFunctionINTEL = 6087,
DecorationMediaBlockIOINTEL = 6140,
DecorationFPMaxErrorINTEL = 6170,
+ DecorationLatencyControlLabelINTEL = 6172,
+ DecorationLatencyControlConstraintINTEL = 6173,
DecorationConduitKernelArgumentINTEL = 6175,
DecorationRegisterMapKernelArgumentINTEL = 6176,
DecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1015,6 +1020,9 @@ enum Capability {
CapabilityRayQueryKHR = 4472,
CapabilityRayTraversalPrimitiveCullingKHR = 4478,
CapabilityRayTracingKHR = 4479,
+ CapabilityTextureSampleWeightedQCOM = 4484,
+ CapabilityTextureBoxFilterQCOM = 4485,
+ CapabilityTextureBlockMatchQCOM = 4486,
CapabilityFloat16ImageAMD = 5008,
CapabilityImageGatherBiasLodAMD = 5009,
CapabilityFragmentMaskAMD = 5010,
@@ -1142,8 +1150,11 @@ enum Capability {
CapabilityOptNoneINTEL = 6094,
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
+ CapabilityBFloat16ConversionINTEL = 6115,
CapabilitySplitBarrierINTEL = 6141,
+ CapabilityFPGAKernelAttributesv2INTEL = 6161,
CapabilityFPMaxErrorDecorationINTEL = 6169,
+ CapabilityFPGALatencyControlINTEL = 6171,
CapabilityFPGAArgumentInterfacesINTEL = 6174,
CapabilityGroupUniformArithmeticKHR = 6400,
CapabilityMax = 0x7fffffff,
@@ -1629,6 +1640,10 @@ enum Op {
OpRayQueryConfirmIntersectionKHR = 4476,
OpRayQueryProceedKHR = 4477,
OpRayQueryGetIntersectionTypeKHR = 4479,
+ OpImageSampleWeightedQCOM = 4480,
+ OpImageBoxFilterQCOM = 4481,
+ OpImageBlockMatchSSDQCOM = 4482,
+ OpImageBlockMatchSADQCOM = 4483,
OpGroupIAddNonUniformAMD = 5000,
OpGroupFAddNonUniformAMD = 5001,
OpGroupFMinNonUniformAMD = 5002,
@@ -1946,6 +1961,8 @@ enum Op {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
@@ -2337,6 +2354,10 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break;
case OpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break;
case OpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break;
+ case OpImageSampleWeightedQCOM: *hasResult = true; *hasResultType = true; break;
+ case OpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break;
+ case OpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break;
+ case OpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break;
case OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
@@ -2649,6 +2670,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index d76a704..0a3defa 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -196,6 +196,7 @@ enum class ExecutionMode : unsigned {
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
StreamingInterfaceINTEL = 6154,
+ RegisterMapInterfaceINTEL = 6160,
NamedBarrierCountINTEL = 6417,
Max = 0x7fffffff,
};
@@ -508,6 +509,8 @@ enum class Decoration : unsigned {
MaxByteOffsetId = 47,
NoSignedWrap = 4469,
NoUnsignedWrap = 4470,
+ WeightTextureQCOM = 4487,
+ BlockMatchTextureQCOM = 4488,
ExplicitInterpAMD = 4999,
OverrideCoverageNV = 5248,
PassthroughNV = 5250,
@@ -577,6 +580,8 @@ enum class Decoration : unsigned {
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
FPMaxErrorINTEL = 6170,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1015,6 +1020,9 @@ enum class Capability : unsigned {
RayQueryKHR = 4472,
RayTraversalPrimitiveCullingKHR = 4478,
RayTracingKHR = 4479,
+ TextureSampleWeightedQCOM = 4484,
+ TextureBoxFilterQCOM = 4485,
+ TextureBlockMatchQCOM = 4486,
Float16ImageAMD = 5008,
ImageGatherBiasLodAMD = 5009,
FragmentMaskAMD = 5010,
@@ -1142,8 +1150,11 @@ enum class Capability : unsigned {
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
+ FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorDecorationINTEL = 6169,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
Max = 0x7fffffff,
@@ -1629,6 +1640,10 @@ enum class Op : unsigned {
OpRayQueryConfirmIntersectionKHR = 4476,
OpRayQueryProceedKHR = 4477,
OpRayQueryGetIntersectionTypeKHR = 4479,
+ OpImageSampleWeightedQCOM = 4480,
+ OpImageBoxFilterQCOM = 4481,
+ OpImageBlockMatchSSDQCOM = 4482,
+ OpImageBlockMatchSADQCOM = 4483,
OpGroupIAddNonUniformAMD = 5000,
OpGroupFAddNonUniformAMD = 5001,
OpGroupFMinNonUniformAMD = 5002,
@@ -1946,6 +1961,8 @@ enum class Op : unsigned {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
@@ -2337,6 +2354,10 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpRayQueryConfirmIntersectionKHR: *hasResult = false; *hasResultType = false; break;
case Op::OpRayQueryProceedKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpRayQueryGetIntersectionTypeKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpImageSampleWeightedQCOM: *hasResult = true; *hasResultType = true; break;
+ case Op::OpImageBoxFilterQCOM: *hasResult = true; *hasResultType = true; break;
+ case Op::OpImageBlockMatchSSDQCOM: *hasResult = true; *hasResultType = true; break;
+ case Op::OpImageBlockMatchSADQCOM: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupIAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFAddNonUniformAMD: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFMinNonUniformAMD: *hasResult = true; *hasResultType = true; break;
@@ -2649,6 +2670,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index 85c775d..04b5f65 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -215,6 +215,7 @@
"NumSIMDWorkitemsINTEL": 5896,
"SchedulerTargetFmaxMhzINTEL": 5903,
"StreamingInterfaceINTEL": 6154,
+ "RegisterMapInterfaceINTEL": 6160,
"NamedBarrierCountINTEL": 6417
}
},
@@ -534,6 +535,8 @@
"MaxByteOffsetId": 47,
"NoSignedWrap": 4469,
"NoUnsignedWrap": 4470,
+ "WeightTextureQCOM": 4487,
+ "BlockMatchTextureQCOM": 4488,
"ExplicitInterpAMD": 4999,
"OverrideCoverageNV": 5248,
"PassthroughNV": 5250,
@@ -603,6 +606,8 @@
"VectorComputeCallableFunctionINTEL": 6087,
"MediaBlockIOINTEL": 6140,
"FPMaxErrorINTEL": 6170,
+ "LatencyControlLabelINTEL": 6172,
+ "LatencyControlConstraintINTEL": 6173,
"ConduitKernelArgumentINTEL": 6175,
"RegisterMapKernelArgumentINTEL": 6176,
"MMHostInterfaceAddressWidthINTEL": 6177,
@@ -995,6 +1000,9 @@
"RayQueryKHR": 4472,
"RayTraversalPrimitiveCullingKHR": 4478,
"RayTracingKHR": 4479,
+ "TextureSampleWeightedQCOM": 4484,
+ "TextureBoxFilterQCOM": 4485,
+ "TextureBlockMatchQCOM": 4486,
"Float16ImageAMD": 5008,
"ImageGatherBiasLodAMD": 5009,
"FragmentMaskAMD": 5010,
@@ -1122,8 +1130,11 @@
"OptNoneINTEL": 6094,
"AtomicFloat16AddEXT": 6095,
"DebugInfoModuleINTEL": 6114,
+ "BFloat16ConversionINTEL": 6115,
"SplitBarrierINTEL": 6141,
+ "FPGAKernelAttributesv2INTEL": 6161,
"FPMaxErrorDecorationINTEL": 6169,
+ "FPGALatencyControlINTEL": 6171,
"FPGAArgumentInterfacesINTEL": 6174,
"GroupUniformArithmeticKHR": 6400
}
@@ -1619,6 +1630,10 @@
"OpRayQueryConfirmIntersectionKHR": 4476,
"OpRayQueryProceedKHR": 4477,
"OpRayQueryGetIntersectionTypeKHR": 4479,
+ "OpImageSampleWeightedQCOM": 4480,
+ "OpImageBoxFilterQCOM": 4481,
+ "OpImageBlockMatchSSDQCOM": 4482,
+ "OpImageBlockMatchSADQCOM": 4483,
"OpGroupIAddNonUniformAMD": 5000,
"OpGroupFAddNonUniformAMD": 5001,
"OpGroupFMinNonUniformAMD": 5002,
@@ -1936,6 +1951,8 @@
"OpTypeStructContinuedINTEL": 6090,
"OpConstantCompositeContinuedINTEL": 6091,
"OpSpecConstantCompositeContinuedINTEL": 6092,
+ "OpConvertFToBF16INTEL": 6116,
+ "OpConvertBF16ToFINTEL": 6117,
"OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitINTEL": 6143,
"OpGroupIMulKHR": 6401,
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index b465bd4..67dff22 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -183,6 +183,7 @@ spv = {
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
StreamingInterfaceINTEL = 6154,
+ RegisterMapInterfaceINTEL = 6160,
NamedBarrierCountINTEL = 6417,
},
@@ -481,6 +482,8 @@ spv = {
MaxByteOffsetId = 47,
NoSignedWrap = 4469,
NoUnsignedWrap = 4470,
+ WeightTextureQCOM = 4487,
+ BlockMatchTextureQCOM = 4488,
ExplicitInterpAMD = 4999,
OverrideCoverageNV = 5248,
PassthroughNV = 5250,
@@ -550,6 +553,8 @@ spv = {
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
FPMaxErrorINTEL = 6170,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -977,6 +982,9 @@ spv = {
RayQueryKHR = 4472,
RayTraversalPrimitiveCullingKHR = 4478,
RayTracingKHR = 4479,
+ TextureSampleWeightedQCOM = 4484,
+ TextureBoxFilterQCOM = 4485,
+ TextureBlockMatchQCOM = 4486,
Float16ImageAMD = 5008,
ImageGatherBiasLodAMD = 5009,
FragmentMaskAMD = 5010,
@@ -1104,8 +1112,11 @@ spv = {
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
+ FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorDecorationINTEL = 6169,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
},
@@ -1580,6 +1591,10 @@ spv = {
OpRayQueryConfirmIntersectionKHR = 4476,
OpRayQueryProceedKHR = 4477,
OpRayQueryGetIntersectionTypeKHR = 4479,
+ OpImageSampleWeightedQCOM = 4480,
+ OpImageBoxFilterQCOM = 4481,
+ OpImageBlockMatchSSDQCOM = 4482,
+ OpImageBlockMatchSADQCOM = 4483,
OpGroupIAddNonUniformAMD = 5000,
OpGroupFAddNonUniformAMD = 5001,
OpGroupFMinNonUniformAMD = 5002,
@@ -1897,6 +1912,8 @@ spv = {
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index a8eb3c9..58664d8 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -183,6 +183,7 @@ spv = {
'NumSIMDWorkitemsINTEL' : 5896,
'SchedulerTargetFmaxMhzINTEL' : 5903,
'StreamingInterfaceINTEL' : 6154,
+ 'RegisterMapInterfaceINTEL' : 6160,
'NamedBarrierCountINTEL' : 6417,
},
@@ -481,6 +482,8 @@ spv = {
'MaxByteOffsetId' : 47,
'NoSignedWrap' : 4469,
'NoUnsignedWrap' : 4470,
+ 'WeightTextureQCOM' : 4487,
+ 'BlockMatchTextureQCOM' : 4488,
'ExplicitInterpAMD' : 4999,
'OverrideCoverageNV' : 5248,
'PassthroughNV' : 5250,
@@ -550,6 +553,8 @@ spv = {
'VectorComputeCallableFunctionINTEL' : 6087,
'MediaBlockIOINTEL' : 6140,
'FPMaxErrorINTEL' : 6170,
+ 'LatencyControlLabelINTEL' : 6172,
+ 'LatencyControlConstraintINTEL' : 6173,
'ConduitKernelArgumentINTEL' : 6175,
'RegisterMapKernelArgumentINTEL' : 6176,
'MMHostInterfaceAddressWidthINTEL' : 6177,
@@ -977,6 +982,9 @@ spv = {
'RayQueryKHR' : 4472,
'RayTraversalPrimitiveCullingKHR' : 4478,
'RayTracingKHR' : 4479,
+ 'TextureSampleWeightedQCOM' : 4484,
+ 'TextureBoxFilterQCOM' : 4485,
+ 'TextureBlockMatchQCOM' : 4486,
'Float16ImageAMD' : 5008,
'ImageGatherBiasLodAMD' : 5009,
'FragmentMaskAMD' : 5010,
@@ -1104,8 +1112,11 @@ spv = {
'OptNoneINTEL' : 6094,
'AtomicFloat16AddEXT' : 6095,
'DebugInfoModuleINTEL' : 6114,
+ 'BFloat16ConversionINTEL' : 6115,
'SplitBarrierINTEL' : 6141,
+ 'FPGAKernelAttributesv2INTEL' : 6161,
'FPMaxErrorDecorationINTEL' : 6169,
+ 'FPGALatencyControlINTEL' : 6171,
'FPGAArgumentInterfacesINTEL' : 6174,
'GroupUniformArithmeticKHR' : 6400,
},
@@ -1580,6 +1591,10 @@ spv = {
'OpRayQueryConfirmIntersectionKHR' : 4476,
'OpRayQueryProceedKHR' : 4477,
'OpRayQueryGetIntersectionTypeKHR' : 4479,
+ 'OpImageSampleWeightedQCOM' : 4480,
+ 'OpImageBoxFilterQCOM' : 4481,
+ 'OpImageBlockMatchSSDQCOM' : 4482,
+ 'OpImageBlockMatchSADQCOM' : 4483,
'OpGroupIAddNonUniformAMD' : 5000,
'OpGroupFAddNonUniformAMD' : 5001,
'OpGroupFMinNonUniformAMD' : 5002,
@@ -1897,6 +1912,8 @@ spv = {
'OpTypeStructContinuedINTEL' : 6090,
'OpConstantCompositeContinuedINTEL' : 6091,
'OpSpecConstantCompositeContinuedINTEL' : 6092,
+ 'OpConvertFToBF16INTEL' : 6116,
+ 'OpConvertBF16ToFINTEL' : 6117,
'OpControlBarrierArriveINTEL' : 6142,
'OpControlBarrierWaitINTEL' : 6143,
'OpGroupIMulKHR' : 6401,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index facf72f..5b94498 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -195,6 +195,7 @@ enum ExecutionMode : uint
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
StreamingInterfaceINTEL = 6154,
+ RegisterMapInterfaceINTEL = 6160,
NamedBarrierCountINTEL = 6417,
}
@@ -509,6 +510,8 @@ enum Decoration : uint
MaxByteOffsetId = 47,
NoSignedWrap = 4469,
NoUnsignedWrap = 4470,
+ WeightTextureQCOM = 4487,
+ BlockMatchTextureQCOM = 4488,
ExplicitInterpAMD = 4999,
OverrideCoverageNV = 5248,
PassthroughNV = 5250,
@@ -578,6 +581,8 @@ enum Decoration : uint
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
FPMaxErrorINTEL = 6170,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1022,6 +1027,9 @@ enum Capability : uint
RayQueryKHR = 4472,
RayTraversalPrimitiveCullingKHR = 4478,
RayTracingKHR = 4479,
+ TextureSampleWeightedQCOM = 4484,
+ TextureBoxFilterQCOM = 4485,
+ TextureBlockMatchQCOM = 4486,
Float16ImageAMD = 5008,
ImageGatherBiasLodAMD = 5009,
FragmentMaskAMD = 5010,
@@ -1149,8 +1157,11 @@ enum Capability : uint
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
+ FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorDecorationINTEL = 6169,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
@@ -1638,6 +1649,10 @@ enum Op : uint
OpRayQueryConfirmIntersectionKHR = 4476,
OpRayQueryProceedKHR = 4477,
OpRayQueryGetIntersectionTypeKHR = 4479,
+ OpImageSampleWeightedQCOM = 4480,
+ OpImageBoxFilterQCOM = 4481,
+ OpImageBlockMatchSSDQCOM = 4482,
+ OpImageBlockMatchSADQCOM = 4483,
OpGroupIAddNonUniformAMD = 5000,
OpGroupFAddNonUniformAMD = 5001,
OpGroupFMinNonUniformAMD = 5002,
@@ -1955,6 +1970,8 @@ enum Op : uint
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 02:13:47 +0000