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authorJohn Kessenich <johnkslang@users.noreply.github.com>2023-03-09 00:22:25 +0700
committerGitHub <noreply@github.com>2023-03-09 00:22:25 +0700
commit9f8e16aa502980acac6c97b8e42204789a97c0fa (patch)
treefb47ae5d4ddce44db5ecb2907abcb43984a30220 /include/spirv/unified1/spv.d
parent647dec7f87a228fccba52e7af7e34d8e260c4ff2 (diff)
parent738a7cc081b29117349444412528a32011d5363a (diff)
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Merge pull request #321 from asudarsa/asudarsa/add_fpga_latency_control_ext
Add support for FPGA latency control extension
Diffstat (limited to 'include/spirv/unified1/spv.d')
-rw-r--r--include/spirv/unified1/spv.d3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index 6f542aa..3b88fc2 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -578,6 +578,8 @@ enum Decoration : uint
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1152,6 +1154,7 @@ enum Capability : uint
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}