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| author | Arvind Sudarsanam <arvind.sudarsanam@intel.com> | 2023-03-08 09:46:03 -0800 |
|---|---|---|
| committer | Arvind Sudarsanam <arvind.sudarsanam@intel.com> | 2023-03-08 09:46:03 -0800 |
| commit | d9d7078e3b8106dba28b5d36e19da3e0f7737d6a (patch) | |
| tree | ed11313c2369a4364533d46bce10466c284bd562 /include/spirv/unified1/spirv.json | |
| parent | f46e295b2062a4e185ba48b0c493415ea3720718 (diff) | |
| parent | 1feaf4414eb2b353764d01d88f8aa4bcc67b60db (diff) | |
| download | SPIRV-Headers-d9d7078e3b8106dba28b5d36e19da3e0f7737d6a.tar.gz SPIRV-Headers-d9d7078e3b8106dba28b5d36e19da3e0f7737d6a.tar.bz2 SPIRV-Headers-d9d7078e3b8106dba28b5d36e19da3e0f7737d6a.zip | |
Merge remote-tracking branch 'real-origin/main' into asudarsa/add_fp_max_error_support
Diffstat (limited to 'include/spirv/unified1/spirv.json')
| -rw-r--r-- | include/spirv/unified1/spirv.json | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json index 85c775d..04b5f65 100644 --- a/include/spirv/unified1/spirv.json +++ b/include/spirv/unified1/spirv.json @@ -215,6 +215,7 @@ "NumSIMDWorkitemsINTEL": 5896, "SchedulerTargetFmaxMhzINTEL": 5903, "StreamingInterfaceINTEL": 6154, + "RegisterMapInterfaceINTEL": 6160, "NamedBarrierCountINTEL": 6417 } }, @@ -534,6 +535,8 @@ "MaxByteOffsetId": 47, "NoSignedWrap": 4469, "NoUnsignedWrap": 4470, + "WeightTextureQCOM": 4487, + "BlockMatchTextureQCOM": 4488, "ExplicitInterpAMD": 4999, "OverrideCoverageNV": 5248, "PassthroughNV": 5250, @@ -603,6 +606,8 @@ "VectorComputeCallableFunctionINTEL": 6087, "MediaBlockIOINTEL": 6140, "FPMaxErrorINTEL": 6170, + "LatencyControlLabelINTEL": 6172, + "LatencyControlConstraintINTEL": 6173, "ConduitKernelArgumentINTEL": 6175, "RegisterMapKernelArgumentINTEL": 6176, "MMHostInterfaceAddressWidthINTEL": 6177, @@ -995,6 +1000,9 @@ "RayQueryKHR": 4472, "RayTraversalPrimitiveCullingKHR": 4478, "RayTracingKHR": 4479, + "TextureSampleWeightedQCOM": 4484, + "TextureBoxFilterQCOM": 4485, + "TextureBlockMatchQCOM": 4486, "Float16ImageAMD": 5008, "ImageGatherBiasLodAMD": 5009, "FragmentMaskAMD": 5010, @@ -1122,8 +1130,11 @@ "OptNoneINTEL": 6094, "AtomicFloat16AddEXT": 6095, "DebugInfoModuleINTEL": 6114, + "BFloat16ConversionINTEL": 6115, "SplitBarrierINTEL": 6141, + "FPGAKernelAttributesv2INTEL": 6161, "FPMaxErrorDecorationINTEL": 6169, + "FPGALatencyControlINTEL": 6171, "FPGAArgumentInterfacesINTEL": 6174, "GroupUniformArithmeticKHR": 6400 } @@ -1619,6 +1630,10 @@ "OpRayQueryConfirmIntersectionKHR": 4476, "OpRayQueryProceedKHR": 4477, "OpRayQueryGetIntersectionTypeKHR": 4479, + "OpImageSampleWeightedQCOM": 4480, + "OpImageBoxFilterQCOM": 4481, + "OpImageBlockMatchSSDQCOM": 4482, + "OpImageBlockMatchSADQCOM": 4483, "OpGroupIAddNonUniformAMD": 5000, "OpGroupFAddNonUniformAMD": 5001, "OpGroupFMinNonUniformAMD": 5002, @@ -1936,6 +1951,8 @@ "OpTypeStructContinuedINTEL": 6090, "OpConstantCompositeContinuedINTEL": 6091, "OpSpecConstantCompositeContinuedINTEL": 6092, + "OpConvertFToBF16INTEL": 6116, + "OpConvertBF16ToFINTEL": 6117, "OpControlBarrierArriveINTEL": 6142, "OpControlBarrierWaitINTEL": 6143, "OpGroupIMulKHR": 6401, |