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authorSidorov, Dmitry <dmitry.sidorov@intel.com>2022-10-17 07:09:36 -0700
committerSidorov, Dmitry <dmitry.sidorov@intel.com>2022-10-17 07:09:36 -0700
commit48d4b677a9bd28af33987580badcbe98ddbaa001 (patch)
treeea2e29a9dae5deff43e1186cef0a50dd21ebdbdd /include/spirv/unified1/spirv.json
parentb3e7b513754ab9eda285f428e817c21feca9b88c (diff)
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Add SPV_INTEL_fpga_dsp_control
Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_fpga_dsp_control.asciidoc Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Diffstat (limited to 'include/spirv/unified1/spirv.json')
-rw-r--r--include/spirv/unified1/spirv.json2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index 281219c..a62f017 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -586,6 +586,7 @@
"PrefetchINTEL": 5902,
"StallEnableINTEL": 5905,
"FuseLoopsInFunctionINTEL": 5907,
+ "MathOpDSPModeINTEL": 5909,
"AliasScopeINTEL": 5914,
"NoAliasINTEL": 5915,
"InitiationIntervalINTEL": 5917,
@@ -1079,6 +1080,7 @@
"FPGAMemoryAccessesINTEL": 5898,
"FPGAClusterAttributesINTEL": 5904,
"LoopFuseINTEL": 5906,
+ "FPGADSPControlINTEL": 5908,
"MemoryAccessAliasingINTEL": 5910,
"FPGAInvocationPipeliningAttributesINTEL": 5916,
"FPGABufferLocationINTEL": 5920,