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authorSidorov, Dmitry <dmitry.sidorov@intel.com>2022-10-17 07:00:53 -0700
committerSidorov, Dmitry <dmitry.sidorov@intel.com>2022-10-17 07:07:25 -0700
commitb3e7b513754ab9eda285f428e817c21feca9b88c (patch)
treedd44124a5c248742004ef72996e1d248b246ff6d /include/spirv/unified1/spirv.cs
parent62269acdbf30e355c320c19e1ba0996ae8cfdf5d (diff)
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Add SPV_INTEL_fpga_invocation_pipelining_attributes
Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_fpga_invocation_pipelining_attributes.asciidoc Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Diffstat (limited to 'include/spirv/unified1/spirv.cs')
-rw-r--r--include/spirv/unified1/spirv.cs4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index c30d351..2c1fd1d 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -560,6 +560,9 @@ namespace Spv
FuseLoopsInFunctionINTEL = 5907,
AliasScopeINTEL = 5914,
NoAliasINTEL = 5915,
+ InitiationIntervalINTEL = 5917,
+ MaxConcurrencyINTEL = 5918,
+ PipelineEnableINTEL = 5919,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -1101,6 +1104,7 @@ namespace Spv
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
MemoryAccessAliasingINTEL = 5910,
+ FPGAInvocationPipeliningAttributesINTEL = 5916,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,