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authorAndrzej Ratajewski <andrzej.ratajewski@intel.com>2023-09-13 17:43:27 +0200
committerGitHub <noreply@github.com>2023-09-13 08:43:27 -0700
commita8af2ce341cfd73a44a37bf62642a2cdf45938df (patch)
tree083d6054cd95b4b8cfe10eff24b34085bc6a17ef /include/spirv/unified1/spirv.cs
parentd790ced752b5bfc06b6988baadef6eb2d16bdf96 (diff)
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Add SPV_INTEL_cache_controls extension support (#376)
Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_cache_controls.asciidoc
Diffstat (limited to 'include/spirv/unified1/spirv.cs')
-rw-r--r--include/spirv/unified1/spirv.cs20
1 files changed, 20 insertions, 0 deletions
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 79369a8..ccf020e 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -613,6 +613,8 @@ namespace Spv
MMHostInterfaceMaxBurstINTEL = 6181,
MMHostInterfaceWaitRequestINTEL = 6182,
StableKernelArgumentINTEL = 6183,
+ CacheControlLoadINTEL = 6442,
+ CacheControlStoreINTEL = 6443,
}
public enum BuiltIn
@@ -1197,6 +1199,7 @@ namespace Spv
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
+ CacheControlsINTEL = 6441,
}
public enum RayFlagsShift
@@ -1350,6 +1353,23 @@ namespace Spv
ReadWriteINTEL = 3,
}
+ public enum LoadCacheControl
+ {
+ UncachedINTEL = 0,
+ CachedINTEL = 1,
+ StreamingINTEL = 2,
+ InvalidateAfterReadINTEL = 3,
+ ConstCachedINTEL = 4,
+ }
+
+ public enum StoreCacheControl
+ {
+ UncachedINTEL = 0,
+ WriteThroughINTEL = 1,
+ WriteBackINTEL = 2,
+ StreamingINTEL = 3,
+ }
+
public enum Op
{
OpNop = 0,