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authorArvind Sudarsanam <arvind.sudarsanam@intel.com>2023-06-09 09:43:46 -0700
committerArvind Sudarsanam <arvind.sudarsanam@intel.com>2023-06-09 09:43:46 -0700
commit33ec2e8a52067da7b6a24821db0f9174579bb5b4 (patch)
tree66ee11a99c767ca796ebea1ea431722df2695117 /include/spirv/unified1/spirv.cs
parent866d16777a54b8a2f7e17aefbd3f479e09df74d4 (diff)
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Interchange capability and decoration
Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
Diffstat (limited to 'include/spirv/unified1/spirv.cs')
-rw-r--r--include/spirv/unified1/spirv.cs4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index a6fe817..38d8800 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -583,7 +583,7 @@ namespace Spv
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
- FPMaxErrorINTEL = 6170,
+ FPMaxErrorDecorationINTEL = 6170,
LatencyControlLabelINTEL = 6172,
LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
@@ -1169,7 +1169,7 @@ namespace Spv
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
- FPMaxErrorDecorationINTEL = 6169,
+ FPMaxErrorINTEL = 6169,
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,