1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
|
// SPDX-License-Identifier: GPL-2.0+
/*
* MTK SATA platform driver
*
* Copyright (C) 2020 MediaTek Inc.
*
* Author: Ryder Lee <ryder.lee@mediatek.com>
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
#include <ahci.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/of_access.h>
#include <generic-phy.h>
#include <linux/err.h>
#include <regmap.h>
#include <reset.h>
#include <sata.h>
#include <scsi.h>
#include <syscon.h>
#include <dm/device_compat.h>
#define SYS_CFG 0x14
#define SYS_CFG_SATA_MSK GENMASK(31, 30)
#define SYS_CFG_SATA_EN BIT(31)
struct mtk_ahci_priv {
void *base;
struct ahci_uc_priv ahci_priv;
struct regmap *mode;
struct reset_ctl_bulk rst_bulk;
};
static int mtk_ahci_bind(struct udevice *dev)
{
struct udevice *scsi_dev;
return ahci_bind_scsi(dev, &scsi_dev);
}
static int mtk_ahci_of_to_plat(struct udevice *dev)
{
struct mtk_ahci_priv *priv = dev_get_priv(dev);
priv->base = devfdt_remap_addr_index(dev, 0);
return 0;
}
static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv,
struct udevice *dev)
{
struct mtk_ahci_priv *plat = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
/* enable SATA function if needed */
if (fdt_get_property(fdt, dev_of_offset(dev),
"mediatek,phy-mode", NULL)) {
plat->mode = syscon_regmap_lookup_by_phandle(dev,
"mediatek,phy-mode");
if (IS_ERR(plat->mode)) {
dev_err(dev, "missing phy-mode phandle\n");
return PTR_ERR(plat->mode);
}
regmap_update_bits(plat->mode, SYS_CFG,
SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN);
}
ofnode_read_u32(dev_ofnode(dev), "ports-implemented",
&hpriv->port_map);
return 0;
}
static int mtk_ahci_probe(struct udevice *dev)
{
struct mtk_ahci_priv *priv = dev_get_priv(dev);
int ret;
struct phy phy;
ret = mtk_ahci_parse_property(&priv->ahci_priv, dev);
if (ret)
return ret;
ret = reset_get_bulk(dev, &priv->rst_bulk);
if (!ret) {
reset_assert_bulk(&priv->rst_bulk);
reset_deassert_bulk(&priv->rst_bulk);
} else {
dev_err(dev, "Failed to get reset: %d\n", ret);
}
ret = generic_phy_get_by_name(dev, "sata-phy", &phy);
if (ret) {
pr_err("can't get the phy from DT\n");
return ret;
}
ret = generic_phy_init(&phy);
if (ret) {
pr_err("unable to initialize the sata phy\n");
return ret;
}
ret = generic_phy_power_on(&phy);
if (ret) {
pr_err("unable to power on the sata phy\n");
return ret;
}
return ahci_probe_scsi(dev, (ulong)priv->base);
}
static const struct udevice_id mtk_ahci_ids[] = {
{ .compatible = "mediatek,mtk-ahci" },
{ }
};
U_BOOT_DRIVER(mtk_ahci) = {
.name = "mtk_ahci",
.id = UCLASS_AHCI,
.of_match = mtk_ahci_ids,
.bind = mtk_ahci_bind,
.of_to_plat = mtk_ahci_of_to_plat,
.ops = &scsi_ops,
.probe = mtk_ahci_probe,
.priv_auto = sizeof(struct mtk_ahci_priv),
};
|
