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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* Author: Ye Li <ye.li@nxp.com>
*/
#include <init.h>
#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/sizes.h>
#include <config.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <usb.h>
#include <usb/ehci-ci.h>
#include <pca953x.h>
DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
return enable_fec_anatop_clock(1, ENET_125MHZ);
}
int board_eth_init(struct bd_info *bis)
{
int ret;
imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
setup_fec();
ret = fecmxc_initialize_multi(bis, 1,
CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
if (ret)
printf("FEC%d MXC: %s:failed\n", 1, __func__);
return ret;
}
int board_phy_config(struct phy_device *phydev)
{
/*
* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
* Phy control debug reg 0
*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
/* rgmii tx clock delay enable */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int power_init_board(void)
{
struct udevice *dev;
int ret;
u32 dev_id, rev_id, i;
u32 switch_num = 6;
u32 offset = PFUZE100_SW1CMODE;
ret = pmic_get("pfuze100", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
return ret;
dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
rev_id = pmic_reg_read(dev, PFUZE100_REVID);
printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
/* Init mode to APS_PFM */
pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
for (i = 0; i < switch_num - 1; i++)
pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
/* set SW1AB staby volatage 0.975V */
pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
/* set SW1C staby volatage 1.10V */
pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
return 0;
}
#ifdef CONFIG_USB_EHCI_MX6
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
/* OGT1 */
MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
/* OTG2 */
MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
};
static void setup_usb(void)
{
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
ARRAY_SIZE(usb_otg_pads));
}
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return usb_phy_mode(port);
}
int board_ehci_hcd_init(int port)
{
u32 *usbnc_usb_ctrl;
if (port > 1)
return -EINVAL;
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);
/* Set Power polarity */
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
return 0;
}
#endif
int board_early_init_f(void)
{
return 0;
}
#ifdef CONFIG_FSL_QSPI
int board_qspi_init(void)
{
/* Set the clock */
enable_qspi_clk(0);
return 0;
}
#endif
#ifdef CONFIG_NAND_MXS
iomux_v3_cfg_t gpmi_pads[] = {
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
};
static void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif
int board_init(void)
{
struct gpio_desc desc;
int ret;
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
ret = dm_gpio_lookup_name("gpio@30_4", &desc);
if (ret)
return ret;
ret = dm_gpio_request(&desc, "cpu_per_rst_b");
if (ret)
return ret;
/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
udelay(500);
dm_gpio_set_value(&desc, 1);
ret = dm_gpio_lookup_name("gpio@32_2", &desc);
if (ret)
return ret;
ret = dm_gpio_request(&desc, "steer_enet");
if (ret)
return ret;
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
udelay(500);
/* Set steering signal to L for selecting B0 */
dm_gpio_set_value(&desc, 0);
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
{"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
{"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
{"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
return 0;
}
int checkboard(void)
{
puts("Board: MX6SX SABRE AUTO\n");
return 0;
}
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