1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
|
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
* Sharma Bhupesh <bhupesh.sharma@freescale.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <dm/platform_data/serial_pl01x.h>
#include "pcie.h"
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct pl01x_serial_platdata serial_platdata = {
.base = V2M_UART0,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
};
U_BOOT_DEVICE(vexpress_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
};
static struct mm_region vexpress64_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0xff80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = vexpress64_mem_map;
/* This function gets replaced by platforms supporting PCIe.
* The replacement function, eg. on Juno, initialises the PCIe bus.
*/
__weak void vexpress64_pcie_init(void)
{
}
int board_init(void)
{
vexpress64_pcie_init();
return 0;
}
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef PHYS_SDRAM_2
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
return 0;
}
#ifdef CONFIG_OF_BOARD
#define JUNO_FLASH_SEC_SIZE (256 * 1024)
static phys_addr_t find_dtb_in_nor_flash(const char *partname)
{
phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
int i;
for (i = 0;
i < CONFIG_SYS_MAX_FLASH_SECT;
i++, sector += JUNO_FLASH_SEC_SIZE) {
int len = strlen(partname) + 1;
int offs;
phys_addr_t imginfo;
u32 reg;
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
/* This makes up the string "HSLFTOOF" flash footer */
if (reg != 0x464F4F54U)
continue;
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
if (reg != 0x464C5348U)
continue;
for (offs = 0; offs < 32; offs += 4, len -= 4) {
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
if (strncmp(partname + offs, (char *)®,
len > 4 ? 4 : len))
break;
if (len > 4)
continue;
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
reg = readl(imginfo + 0x54);
return CONFIG_SYS_FLASH_BASE +
reg * JUNO_FLASH_SEC_SIZE;
}
}
printf("No DTB found\n");
return ~0;
}
void *board_fdt_blob_setup(void)
{
phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
if (fdt_rom_addr == ~0UL)
return NULL;
return (void *)fdt_rom_addr;
}
#endif
/* Actual reset is done via PSCI. */
void reset_cpu(ulong addr)
{
}
/*
* Board specific ethernet initialization routine.
*/
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC91111
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
|
