From f34ccce50a1805a6fdb2d1604ec4e40d79302455 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 12 Jun 2017 17:50:55 +0800 Subject: mmc: fsl_esdhc: drop CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT is not the correct method to set I/O to 1.8. To boards that does not support vqmmc-supply, use vs18_enable in fsl_esdhc_cfg. If regulator is supported, use fixed 1.8V regulator for vqmmc-supply. Signed-off-by: Peng Fan Cc: Jaehoon Chung Cc: York Sun Cc: Stefano Babic --- doc/README.fsl-esdhc | 2 -- 1 file changed, 2 deletions(-) (limited to 'doc/README.fsl-esdhc') diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc index 7e71387576..29cc6619ea 100644 --- a/doc/README.fsl-esdhc +++ b/doc/README.fsl-esdhc @@ -20,5 +20,3 @@ Freescale esdhc-specific options - CONFIG_SYS_FSL_ESDHC_BE ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. - - - CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. -- cgit v1.2.3