From efbb3d491e87935421242396958fdddd87e0fde1 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 18 Jul 2016 13:02:11 -0600 Subject: ARM: tegra: p2371-2180: A03 board PMIC config update Rev A03 of P2180 requires some PMIC programming adjustments, yet the PMIC's own OTP has not been updated. Consequently, U-Boot must make these changes itself. NVIDIA's syseng team has confirmed that these changes can be enabled on all board revisions without issue. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- board/nvidia/p2371-2180/p2371-2180.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'board/nvidia/p2371-2180') diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 0f587eaaa7..dbdc1b65e6 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -30,6 +30,28 @@ void pin_mux_mmc(void) ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + + /* Disable LDO4 discharge */ + ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) { + printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); + } else { + val &= ~BIT(1); /* ADE */ + ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); + } + + /* Set MBLPD */ + ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } else { + val |= BIT(6); /* MBLPD */ + ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } } /* -- cgit v1.2.3