From fe60f06dcdee82b41f47e56ccb99cced91f1d2ac Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Tue, 13 Sep 2016 10:45:58 -0600
Subject: reset: implement a driver for the Tegra CAR

Implement a reset uclass driver for the Tegra CAR. This allows clients to
use standard reset APIs on Tegra. This device is intended to be
instantiated by the core Tegra CAR driver, rather than being instantiated
directly from DT. The implementation uses the existing custom Tegra-
specific reset APIs to avoid coupling the series with significant
refactoring of the existing Tegra clock/reset code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 drivers/reset/Kconfig           |  7 ++++
 drivers/reset/Makefile          |  1 +
 drivers/reset/tegra-car-reset.c | 72 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 80 insertions(+)
 create mode 100644 drivers/reset/tegra-car-reset.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 5b84f2178b..4fcc0d95b4 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -20,6 +20,13 @@ config SANDBOX_RESET
 	  simply accepts requests to reset various HW modules without actually
 	  doing anything beyond a little error checking.
 
+config TEGRA_CAR_RESET
+	bool "Enable Tegra CAR-based reset driver"
+	depends on TEGRA_CAR
+	help
+	  Enable support for manipulating Tegra's on-SoC reset signals via
+	  direct register access to the Tegra CAR (Clock And Reset controller).
+
 config TEGRA186_RESET
 	bool "Enable Tegra186 BPMP-based reset driver"
 	depends on TEGRA186_BPMP
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index ff0e090775..5d4ea3d79d 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,4 +5,5 @@
 obj-$(CONFIG_DM_RESET) += reset-uclass.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
diff --git a/drivers/reset/tegra-car-reset.c b/drivers/reset/tegra-car-reset.c
new file mode 100644
index 0000000000..3147a50853
--- /dev/null
+++ b/drivers/reset/tegra-car-reset.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+
+static int tegra_car_reset_request(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	/* PERIPH_ID_COUNT varies per SoC */
+	if (reset_ctl->id >= PERIPH_ID_COUNT)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int tegra_car_reset_free(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	return 0;
+}
+
+static int tegra_car_reset_assert(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	reset_set_enable(reset_ctl->id, 1);
+
+	return 0;
+}
+
+static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+	      reset_ctl->dev, reset_ctl->id);
+
+	reset_set_enable(reset_ctl->id, 0);
+
+	return 0;
+}
+
+struct reset_ops tegra_car_reset_ops = {
+	.request = tegra_car_reset_request,
+	.free = tegra_car_reset_free,
+	.rst_assert = tegra_car_reset_assert,
+	.rst_deassert = tegra_car_reset_deassert,
+};
+
+static int tegra_car_reset_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(tegra_car_reset) = {
+	.name = "tegra_car_reset",
+	.id = UCLASS_RESET,
+	.probe = tegra_car_reset_probe,
+	.ops = &tegra_car_reset_ops,
+};
-- 
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