From b0e2b6abac0fe1f497a2ba9c24f8376a57700547 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Mon, 22 Aug 2022 11:39:43 -0700 Subject: arm: bcmbca: add bcm6858 SoC support under CONFIG_ARCH_BCMBCA BCM6858 is a Broadcom B53 based PON Gateway SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family. Like other broadband SoC, this patch adds it under CONFIG_BCM6858 chip config and CONFIG_ARCH_BCMBCA platform config. This initial support includes a bare-bone implementation and the original dts is updated with the one from linux next git repository. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there to the console. Signed-off-by: William Zhang Reviewed-by: Philippe Reynes --- MAINTAINERS | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/bcm6858.dtsi | 197 ++++++++++++++++++------------- arch/arm/dts/bcm96858.dts | 30 +++++ arch/arm/mach-bcmbca/Kconfig | 11 ++ arch/arm/mach-bcmbca/Makefile | 1 + arch/arm/mach-bcmbca/bcm6858/Kconfig | 17 +++ arch/arm/mach-bcmbca/bcm6858/Makefile | 5 + arch/arm/mach-bcmbca/bcm6858/mmu_table.c | 32 +++++ board/broadcom/bcmbca/Kconfig | 7 ++ configs/bcm96858_defconfig | 23 ++++ include/configs/bcm96858.h | 11 ++ 12 files changed, 258 insertions(+), 79 deletions(-) create mode 100644 arch/arm/dts/bcm96858.dts create mode 100644 arch/arm/mach-bcmbca/bcm6858/Kconfig create mode 100644 arch/arm/mach-bcmbca/bcm6858/Makefile create mode 100644 arch/arm/mach-bcmbca/bcm6858/mmu_table.c create mode 100644 configs/bcm96858_defconfig create mode 100644 include/configs/bcm96858.h diff --git a/MAINTAINERS b/MAINTAINERS index 8064e9bbfa..e86ffc0e3f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -230,6 +230,7 @@ N: bcm[9]?6756 N: bcm[9]?6813 N: bcm[9]?6846 N: bcm[9]?6856 +N: bcm[9]?6858 N: bcm[9]?6878 ARM BROADCOM BCMSTB diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8d1e969d1c..37659cbf33 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1199,6 +1199,8 @@ dtb-$(CONFIG_BCM6846) += \ dtb-$(CONFIG_BCM6856) += \ bcm96856.dtb \ bcm968360bg.dtb +dtb-$(CONFIG_BCM6858) += \ + bcm96858.dtb dtb-$(CONFIG_BCM6878) += \ bcm96878.dtb diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index 0222562171..19c4dd6fa7 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -1,122 +1,161 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018 Philippe Reynes + * Copyright 2022 Broadcom Ltd. */ -#include "skeleton64.dtsi" +#include +#include / { - compatible = "brcm,bcm6858"; + compatible = "brcm,bcm6858", "brcm,bcmbca"; #address-cells = <2>; #size-cells = <2>; - aliases { - spi0 = &hsspi; - }; + interrupt-parent = <&gic>; cpus { #address-cells = <2>; #size-cells = <0>; - u-boot,dm-pre-reloc; - cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x0>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x1>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x2>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x3>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - l2: l2-cache0 { + L2_0: l2-cache0 { compatible = "cache"; - u-boot,dm-pre-reloc; }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + clocks { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; u-boot,dm-pre-reloc; - periph_osc: periph-osc { + periph_clk: periph_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; - u-boot,dm-pre-reloc; }; hsspi_pll: hsspi-pll { compatible = "fixed-factor-clock"; #clock-cells = <0>; - clocks = <&periph_osc>; + clocks = <&periph_clk>; clock-mult = <2>; clock-div = <1>; }; - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; + wdt_clk: wdt-clk { + compatible = "fixed-factor-clock"; #clock-cells = <0>; - clock-frequency = <50000000>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; }; }; - ubus { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, /* GICD */ + <0x2000 0x2000>, /* GICC */ + <0x4000 0x2000>, /* GICH */ + <0x6000 0x2000>; /* GICV */ + interrupts = ; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; u-boot,dm-pre-reloc; - uart0: serial@ff800640 { + uart0: serial@640 { compatible = "brcm,bcm6345-uart"; - reg = <0x0 0xff800640 0x0 0x18>; - clocks = <&periph_osc>; - + reg = <0x640 0x18>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "refclk"; status = "disabled"; }; - leds: led-controller@ff800800 { + leds: led-controller@800 { compatible = "brcm,bcm6858-leds"; - reg = <0x0 0xff800800 0x0 0xe4>; + reg = <0x800 0xe4>; status = "disabled"; }; - wdt1: watchdog@ff802780 { + wdt1: watchdog@2780 { compatible = "brcm,bcm6345-wdt"; - reg = <0x0 0xff802780 0x0 0x14>; - clocks = <&refclk50mhz>; + reg = <0x2780 0x14>; + clocks = <&wdt_clk>; }; - wdt2: watchdog@ff8027c0 { + wdt2: watchdog@27c0 { compatible = "brcm,bcm6345-wdt"; - reg = <0x0 0xff8027c0 0x0 0x14>; - clocks = <&refclk50mhz>; + reg = <0x27c0 0x14>; + clocks = <&wdt_clk>; }; wdt-reboot { @@ -124,91 +163,91 @@ wdt = <&wdt1>; }; - gpio0: gpio-controller@0xff800500 { + gpio0: gpio-controller@500 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800500 0x0 0x4>, - <0x0 0xff800520 0x0 0x4>; + reg = <0x500 0x4>, + <0x520 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio1: gpio-controller@0xff800504 { + gpio1: gpio-controller@504 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800504 0x0 0x4>, - <0x0 0xff800524 0x0 0x4>; + reg = <0x504 0x4>, + <0x524 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio2: gpio-controller@0xff800508 { + gpio2: gpio-controller@508 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800508 0x0 0x4>, - <0x0 0xff800528 0x0 0x4>; + reg = <0x508 0x4>, + <0x528 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio3: gpio-controller@0xff80050c { + gpio3: gpio-controller@50c { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff80050c 0x0 0x4>, - <0x0 0xff80052c 0x0 0x4>; + reg = <0x50c 0x4>, + <0x52c 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio4: gpio-controller@0xff800510 { + gpio4: gpio-controller@510 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800510 0x0 0x4>, - <0x0 0xff800530 0x0 0x4>; + reg = <0x510 0x4>, + <0x530 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio5: gpio-controller@0xff800514 { + gpio5: gpio-controller@514 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800514 0x0 0x4>, - <0x0 0xff800534 0x0 0x4>; + reg = <0x514 0x4>, + <0x534 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio6: gpio-controller@0xff800518 { + gpio6: gpio-controller@518 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800518 0x0 0x4>, - <0x0 0xff800538 0x0 0x4>; + reg = <0x518 0x4>, + <0x538 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio7: gpio-controller@0xff80051c { + gpio7: gpio-controller@51c { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff80051c 0x0 0x4>, - <0x0 0xff80053c 0x0 0x4>; + reg = <0x51c 0x4>, + <0x53c 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - hsspi: spi-controller@ff801000 { + hsspi: spi-controller@1000 { compatible = "brcm,bcm6328-hsspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0xff801000 0x0 0x600>; + reg = <0x1000 0x600>; clocks = <&hsspi_pll>, <&hsspi_pll>; clock-names = "hsspi", "pll"; spi-max-frequency = <100000000>; @@ -217,14 +256,14 @@ status = "disabled"; }; - nand: nand-controller@ff801800 { + nand: nand-controller@1800 { compatible = "brcm,nand-bcm6858", "brcm,brcmnand-v5.0", "brcm,brcmnand"; reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x0 0xff801800 0x0 0x180>, - <0x0 0xff802000 0x0 0x10>, - <0x0 0xff801c00 0x0 0x200>; + reg = <0x1800 0x180>, + <0x2000 0x10>, + <0x1c00 0x200>; parameter-page-big-endian = <0>; status = "disabled"; diff --git a/arch/arm/dts/bcm96858.dts b/arch/arm/dts/bcm96858.dts new file mode 100644 index 0000000000..0cbf582f5d --- /dev/null +++ b/arch/arm/dts/bcm96858.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6858.dtsi" + +/ { + model = "Broadcom BCM96858 Reference Board"; + compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index f35f02c597..5b977734df 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -93,6 +93,16 @@ config BCM6856 Broadcom BCM6856 is a dual core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6856, BCM6836 and BCM4910. +config BCM6858 + bool "Support for Broadcom 6858 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select BCM6345_SERIAL + help + Broadcom BCM6858 is a quad core Brahma-B53 ARMv8 based xPON Gateway + SoC. This SoC family includes BCM6858, BCM49508, BCM5504X and BCM6545. + config BCM6878 bool "Support for Broadcom 6878 Family" select SYS_ARCH_TIMER @@ -112,6 +122,7 @@ source "arch/arm/mach-bcmbca/bcm6756/Kconfig" source "arch/arm/mach-bcmbca/bcm6813/Kconfig" source "arch/arm/mach-bcmbca/bcm6846/Kconfig" source "arch/arm/mach-bcmbca/bcm6856/Kconfig" +source "arch/arm/mach-bcmbca/bcm6858/Kconfig" source "arch/arm/mach-bcmbca/bcm6878/Kconfig" endif diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile index 20f8275120..c068094174 100644 --- a/arch/arm/mach-bcmbca/Makefile +++ b/arch/arm/mach-bcmbca/Makefile @@ -15,4 +15,5 @@ obj-$(CONFIG_BCM6756) += bcm6756/ obj-$(CONFIG_BCM6813) += bcm6813/ obj-$(CONFIG_BCM6846) += bcm6846/ obj-$(CONFIG_BCM6856) += bcm6856/ +obj-$(CONFIG_BCM6858) += bcm6858/ obj-$(CONFIG_BCM6878) += bcm6878/ diff --git a/arch/arm/mach-bcmbca/bcm6858/Kconfig b/arch/arm/mach-bcmbca/bcm6858/Kconfig new file mode 100644 index 0000000000..a6504bae1f --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6858/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6858 + +config TARGET_BCM96858 + bool "Broadcom 6858 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6858" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6858/Makefile b/arch/arm/mach-bcmbca/bcm6858/Makefile new file mode 100644 index 0000000000..6262497703 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6858/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c new file mode 100644 index 0000000000..898291075f --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include +#include +#include + +static struct mm_region bcm96858_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm96858_mem_map; diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig index efe504919a..7da9e954d4 100644 --- a/board/broadcom/bcmbca/Kconfig +++ b/board/broadcom/bcmbca/Kconfig @@ -93,6 +93,13 @@ config SYS_CONFIG_NAME endif +if TARGET_BCM96858 + +config SYS_CONFIG_NAME + default "bcm96858" + +endif + if TARGET_BCM96878 config SYS_CONFIG_NAME diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig new file mode 100644 index 0000000000..5f7be1107e --- /dev/null +++ b/configs/bcm96858_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=50000000 +CONFIG_ARCH_BCMBCA=y +CONFIG_SYS_TEXT_BASE=0x01000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_BCM6858=y +CONFIG_TARGET_BCM96858=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="bcm96858" +CONFIG_IDENT_STRING=" Broadcom BCM6858" +CONFIG_SYS_LOAD_ADDR=0x01000000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_CMD_CACHE=y +CONFIG_OF_EMBED=y +CONFIG_CLK=y diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h new file mode 100644 index 0000000000..4e584b41fb --- /dev/null +++ b/include/configs/bcm96858.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2022 Broadcom Ltd. + */ + +#ifndef __BCM96858_H +#define __BCM96858_H + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +#endif -- cgit v1.2.3