summaryrefslogtreecommitdiff
path: root/include
AgeCommit message (Collapse)AuthorFilesLines
2015-07-22include: usb: Map USB controller base addresses for LS2085ANikhil Badola1-0/+3
Map USB XHCI controller base addresses for LS2085A SOC Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
2015-07-22include: usb: Move USB controller base address mappingNikhil Badola1-0/+7
Move USB controller Base address mapping from ls102xa immap to fsl xhci header. This is required to remove any warnings when controller base addresses are mapped for multiple platforms in their respective files. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
2015-07-22drivers: usb: fsl: Implement Erratum A-009116 for XHCI controllerNikhil Badola1-6/+16
This adjusts (micro)frame length to appropriate value thus avoiding USB devices to time out over a longer run Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
2015-07-22ls1021aqds: Enable USB IP supportRamneek Mehresh1-5/+17
Enable USB IP support for both EHCI and XHCI for ls1021aqds platform Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2015-07-22ls1021atwr: Enable USB IP supportRamneek Mehresh1-0/+38
Enable USB IP support for both EHCI and XHCI for ls1021atwr platform Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2015-07-22usb: fsl: Add XHCI driver supportRamneek Mehresh1-0/+54
Add xhci driver support for all FSL socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2015-07-22usb: xhci: keystone: Remove common dwc3 drv functions callsRamneek Mehresh1-0/+1
Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2015-07-22usb: xhci: omap: Remove common dwc3 drv functions callsRamneek Mehresh3-0/+3
Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2015-07-22usb: xhci: exynos: Remove common dwc3 drv functions callsRamneek Mehresh1-0/+1
Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2015-07-22usb: dwc3: Add DWC3 controller driver supportRamneek Mehresh1-0/+6
Add support for DWC3 XHCI controller driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2015-07-20Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini13-75/+299
2015-07-20armv8/ls2085ardb: Enable DSPI flash support for LS2085ARDBHaikun Wang1-0/+8
Enable DSPI flash related configurations for LS2085ARDB. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085aqds: Enable DSPI flash support for LS2085AQDSHaikun Wang1-0/+9
Enable DSPI flash related configurations. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20arm/ls102xa: Add PSCI support for ls102xaWang Dongsheng2-0/+4
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20board/ls2085a: Increase kernel_size value in env variablePrabhakar Kushwaha3-3/+3
Linux itb image size has been increased from 30MB. So updating kernel_size to 40MB in env variable. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20board/ls2085rdb: Export functions for standalone AQ FW load appsPrabhakar Kushwaha3-1/+26
Export functions required by Aquntia PHY firmware load application. functions are memset, strcpy, mdelay, mdio_get_current_dev, phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/fsl-lsch3: partition stream IDsStuart Yoder2-4/+1
Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20drivers: fsl-mc: Update flibs to mc-0.6.0.1Prabhakar Kushwaha5-52/+191
Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in dpio_attr. These are now offsets from the SoC QBMan portals base. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20drivers/fsl-mc: Autoload AOIP image from NOR flashJ. German Rivera3-0/+6
Load AIOP image from NOR flash into DDR so that the MC firmware the MC fw can start it at boot time Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085a: enable debug serverStuart Yoder1-0/+1
Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvrPrabhakar Kushwaha1-3/+9
The agreed split of the top of memory is 256M for debug server and 256M for MC. This patch implements the split. In addition, the MC mem must be 512MB aligned, so the amount of memory to hide must be 512MB to achieve that alignment. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085ardb: Fix SPD address error on early boardsYork Sun1-2/+2
Board rev C and earlier has duplicated SPD address on 2nd DDR controller slots. It is fixed on rev D and later. SPD addresses need to be updated accordingly. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-07-20driver/ddr/fsl: Add a hook to update SPD addressYork Sun1-0/+3
In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-07-20armv8/ls2085a: Avoid hard-coding for board name printPrabhakar Kushwaha2-5/+0
LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A personlities. Instead of hard-coding, board name should change as per selected personality. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085a: Increase the supported kernel sizeBhupesh Sharma3-5/+8
Increases the kernel size supported for LS2085A platforms:- - Update environment variables - Add ramdisk_size in bootargs env variable - Define CONFIG_SYS_BOOTM_LEN to 64MB Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085rdb: Update PCA9547PW slave addressPrabhakar Kushwaha1-2/+2
Primary Mux on I2C1 controller has slave address as 0x75. So update its address. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085a: Update LS2085a PCIe compatiblePrabhakar Kushwaha1-1/+2
Compatible field "fsl,20851a-pcie" is not correct. So update it to "fsl,ls2085a-pcie" Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085a: Enable "date" command for QDS and RDBPriyanka Jain2-0/+2
Enable "date" command for QDS and RDB boards Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085ardb: add hwconfig setting for eSDHCYangbo Lu1-0/+2
Add hwconfig setting for eSDHC since it shares some pins with other IP block. Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085ardb: Add eth & phy firmware loading supportPrabhakar Kushwaha1-0/+23
Add support for board eth initialization and support for loading phy firmware. PHY firmware needs to be loaded from board_eth_init() because all the MACs are not initialized by ldpaa_eth driver. Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20libfdt: fix description of fdt_get_string()Masahiro Yamada1-1/+1
Looks like this comment was copied from that of fdt_get_string_index(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Fixes: 5094eb408a5d ("fdt: Add functions to retrieve strings") Acked-by: Simon Glass <sjg@chromium.org>
2015-07-20fdt: prevent clearing memory node if there are no banksAndre Przywara1-0/+26
Avoid clearing the reg property in the memory DT node if no memory banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0). This allows boards to let U-Boot skip the DT memory tinkering in case other firmware has already setup the node properly before. This should be safe as all callers of fdt_fixup_memory_banks that use a computed <banks> value put at least 1 in there. Add some documentation comments to the header file. Signed-off-by: Andre Przywara <osp@andrep.de> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-15Merge git://git.denx.de/u-boot-x86Tom Rini7-27/+39
2015-07-14pci: Configure expansion ROM during auto config processBin Meng1-9/+0
Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass1-0/+1
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14dm: x86: minnowmax: Move PCI to use driver modelSimon Glass1-0/+1
Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-14dm: spi: Enable environment for minnowmaxSimon Glass1-3/+2
Enable a SPI environment and store it in a suitable place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-07-14x86: Configure VESA parameters before loading Linux kernelBin Meng1-2/+2
Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
2015-07-14x86: crownbay: Enable graphics supportBin Meng1-7/+7
Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14x86: Move VGA option rom macros to KconfigBin Meng2-6/+0
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14dm: pci: Use the correct hose when configuring devicesSimon Glass1-0/+10
Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-14dm: cpu: Add a new get_count method to cpu uclassBin Meng1-0/+16
Introduce a new method 'get_count' in the UCLASS_CPU ops to get the number of CPUs in the system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-14Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini1-3/+18
2015-07-10Merge git://git.denx.de/u-boot-marvellTom Rini1-0/+41
2015-07-10mtd: fix false positive "Offset exceeds device limit" errorMasahiro Yamada1-2/+3
Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-07-10arm: mvebu: db-88f6820-gp: Add USB/EHCI supportStefan Roese1-0/+7
This patch enabled the USB/EHCI support for the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10arm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) supportStefan Roese1-0/+11
Configure and enable the SATA/SCSI (AHCI) support for the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38xStefan Roese1-0/+1
This patch adds support for the common AHCI controller on the Marvell Armada 38x. Tested on the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10arm: mvebu: db-88f6820-gp: Add MMC/SDIO supportStefan Roese1-0/+22
This patch adds MMC/SDIO support to the Marvell DB-88F6820-GP board configuration. Including support for the common partitions and filesystems. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-09ahci: Fix compiling warnings under 64bit platformsTang Yuantian1-4/+4
When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; ^ drivers/block/ahci.c: In function ?.hci_host_init?. drivers/block/ahci.c:218:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); ...... Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 15:26:55 +0000