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2020-07-28Convert CONFIG_SPL_NAND_DRIVERS et al to KconfigAdam Ford26-42/+0
This converts the following to Kconfig: CONFIG_SPL_NAND_DRIVERS CONFIG_SPL_NAND_ECC CONFIG_SPL_NAND_SIMPLE Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-28Convert CONFIG_ENV_OVERWRITE to KconfigAdam Ford198-351/+0
This converts the following to Kconfig: CONFIG_ENV_OVERWRITE Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rerun migration, remove some comments] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini18-35/+73
- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a - lx2-watchdog support - layerscape: pci-endpoint support, spin table relocation fixes and cleanups - fsl-crypto: RNG support and bug fixes
2020-07-27Merge tag 'dm-pull-20jul20-take2a' of ↵Tom Rini4-47/+154
https://gitlab.denx.de/u-boot/custodians/u-boot-dm binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
2020-07-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini3-0/+187
- R8A774A1 / Beacon EmbeddedWorks RZG2M Dev Kit support
2020-07-27Merge branch 'net' of https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini19-19/+0
- Convert dc2114x driver to DM.
2020-07-27pci_ep: Add the init functionXiaowei Bao1-0/+1
Some EP deivces need to initialize before RC scan it, e.g. NXP layerscape platform, so add the init function in pci_ep uclass. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: instantiate the RNG with prediciton resistanceMichael Walle1-4/+3
If it is already instantiated tear it down first and then reinstanciate it again with prediction resistance. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: don't regenerate secure keysMichael Walle1-0/+1
The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a POR. Otherwise the RNG4 will throw an error. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: support newer SEC modulesMichael Walle1-7/+44
Since Era 10, the version registers changed. Add the version registers and use them on newer modules. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27crypto/fsl: export caam_get_era()Michael Walle1-0/+2
We need the era in other modules, too. For example, to get the RNG version. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN valueKuldeep Singh1-1/+2
Previous attempt to increase CONFIG_SYS_MALLOC_LEN was done in commit c084a8edf4e2 ("configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size") which increased malloc memory to ~1M. PFE firmware alone requires 3M of dynamic memory allocation and therefore, increase the config value to a larger value i.e 5M. This size should be enough as of now to accommodate further memory requirements. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27Move eSDHC adapter card identification to board filesYangbo Lu2-5/+0
The eSDHC adapter card identification and multiplexing configuration through FPGA had been implemented in both common mmc driver and fsl_esdhc driver. However it is proper to move these code to board files and do it during board initialization. The FPGA registers are also board specific. This patch is to move eSDHC adapter card identification and multiplexing configuration from mmc driver to specific board files. And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> [Rebased, Removed T1040QDS change as board does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: ls1028ardb: add xspi parameter to qixis commandYuantian Tang1-2/+2
Add xspi boot source to qixis command to let the soc boot from flex-nor flash chip. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27include/configs: ls1012a: Remove fdt_high env variableUdit Agarwal5-5/+5
Remove "fdt_high" environment variable to use the bootm_size to safely contain a kernel, device tree and initrd for relocation. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27I2C: ls1043a, ls1046a: enable SYS_I2C_MXCBiwen Li2-3/+1
This enables SYS_I2C_MXC to fix a bug that failed to boot from sd card with image u-boot-with-spl-pbl.bin Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: layerscape: properly use CPU_RELEASE_ADDRMichael Walle6-6/+6
The generic armv8 code already has support to bring up the secondary cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to the spin table code; instead just return early and let the common armv8 code handle the jump. This way we can actually use the CPU_RELEASE_ADDR feature. Signed-off-by: Michael Walle <michael@walle.cc> [Rebased, Removed kontron_sl28.h change as file does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27net: pfe_eth: Use spi_flash_read API to access flash memoryKuldeep Singh1-1/+4
Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27configs: ls1088ardb: Add support for usb boot targetEra Tiwari1-0/+1
LS1088A-RDB has MMC, SCSI, DHCP as boot targets, but the USB support was missing. Add support for USB as Boot_targets_devices. Signed-off-by: Era Tiwari <era.tiwari@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27armv8: ls1028a: move FSL_LAYERSCAPE to kconfigMichael Walle1-1/+0
CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to define it per board; the ls1028a_common.h is really board dependent and only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE when ARCH_LS1028A is selected. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delaysVladimir Oltean1-0/+1
Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-26cmd: env: check real location for env info commandPatrick Delaunay1-0/+11
Check the current ENV location, dynamically provided by the weak function env_get_location to be sure that the environment can be persistent. The compilation flag ENV_IS_IN_DEVICE is not enough when the board dynamically select the available storage location (according boot device for example). This patch solves issue for stm32mp1 platform, when the boot device is USB. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-25dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matchingDave Gerlach2-0/+146
Introduce UCLASS_SOC to be used for SOC identification and attribute matching based on the SoC ID info. This allows drivers to be provided for SoCs to retrieve SoC identifying information and also for matching device attributes for selecting SoC specific data. This is useful for other device drivers that may need different parameters or quirks enabled depending on the specific device variant in use. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25Revert "lib: fdt: Split fdtdec_setup_mem_size_base()"Michal Simek1-20/+0
This reverts commit 3ebe09d09a407f93022d945a205c5318239eb3f6. There is no user of this split function that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-25Revert "lib: fdt: Split fdtdec_setup_memory_banksize()"Michal Simek1-19/+0
This reverts commit 118f4d4559a4386fa87a1e2509e84a1986b24a34. There is no user of this split function that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-25cpu: Convert the methods to use a const udevice *Simon Glass1-8/+8
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-25ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev KitAdam Ford1-0/+89
The Beacon EmbeddedWorks kit is based on the R8A774A1 SoC also known as the RZ/G2M. The kit consists of a SOM + Baseboard and supports microSD, eMMC, Ethernet, a couple celular radios, two CAN interfaces, Bluetooth and WiFi. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25net: dc2114x: Add Kconfig entriesMarek Vasut19-19/+0
Add Kconfig entries for the dc2114x driver and convert various boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
2020-07-25ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1Adam Ford2-0/+98
This patch imports the device tree and required bindings to permit the device tree to build for the R8Z774A1 (RZ/G2M). Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-24Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini1-1/+6
- Fix SiFive HiFive Unleashed board booting failure problem. - Enable SiFive fu540 PWM driver. - Support SiFive fu540: SPI boot. - Update OpenSBI used for RISC-V CI testing. - Revert "riscv: Allow use of reset drivers". - Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"". - sysreset: syscon: - Don't assume default value for offset and mask property. - Support value property. - qemu: Add syscon reboot and poweroff support. - Fix SIFIVE debug serial dependency. - Fix linking error when building u-boot-spl with no SMP support. - AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg. - Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi - SiFive fu540 avoid using hardcoded ram base and size.
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini4-154/+47
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24sifive: fu540: Enable SF distro bootcmdJagan Teki1-1/+4
Enable SPI flash(SF) distro boot command in Sifive FU540. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-24sifive: fu540: Add boot flash script offset, sizeJagan Teki1-0/+2
HiFive-Unleashed-A00 has SPI flash with 32MiB size. So, let's use the script offset at the end of 4K. This way it cannot overlap any offsets being used by software components in flash layout. So, SF distrocmd will pick the script at desired script address and run. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-23Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dmTom Rini4-47/+154
binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
2020-07-23Merge tag 'efi-2020-10-rc1-5' of ↵Tom Rini3-10/+17
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-10-rc1 (5) The series provides bug fixes for: * crash in OS when accessing UEFI variables * returning from UEFI fit images to U-Boot * error handling for variable services provided by OP-TEE * error handling in EFI_FILE_PROTOCOL.Read() * missing function documentation The first patches needed to use intermediate certificates for secure boot are added. (The rest of the series requires updating sbsigntool in our CI systems.) Logging is enabled in the bootefi command.
2020-07-22Merge tag 'u-boot-rockchip-20200722' of ↵Tom Rini3-2/+25
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New rk3326 board: Hardkernel Odroid Go2; - Update board config and dts for RockPI 4/N8/N10; - Update led boot on support for roc-rk3399-pc; - Enable SPI Flash suppor for rk3328 rock64 board; - Update rockchip pcie phy to use generic framework;
2020-07-22rockchip: evb_rk3288: Add console settingsSuniel Mahesh1-1/+5
Add console settings like stdin, stdout and stderr as usbkbd and vidconsole respectively for evb-rk3288 targets. This would certainly help to detect the attached video devices (like HDMI) and print the console messages on display. Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: rk3399: Add default env to support compressed kernel ImageKever Yang1-1/+3
Add default kernel_comp_addr_r and kernel_comp_size to support boot from compressed kernel Image, this space is temporarily used during decompress according to README.distro. Reported-by: Tian Yuanhao <tianyuanhao@aliyun.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: board: add Hardkernel Odroid Go2 boardHeiko Stuebner1-0/+17
Also known as Odroid Go Advance but named Go2 internally by the vendor it seems. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22lib: crypto: export and enhance pkcs7_verify_one()AKASHI Takahiro1-1/+8
The function, pkcs7_verify_one(), will be utilized to rework signature verification logic aiming to support intermediate certificates in "chain of trust." To do that, its function interface is expanded, adding an extra argument which is expected to return the last certificate in trusted chain. Then, this last one must further be verified with signature database, db and/or dbx. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2020-07-22lib: crypto: add public_key_verify_signature()AKASHI Takahiro1-1/+1
This function will be called from x509_check_for_self_signed() and pkcs7_verify_one(), which will be imported from linux in a later patch. While it does exist in linux code and has a similar functionality of rsa_verify(), it calls further linux-specific interfaces inside. That could lead to more files being imported from linux. So simply re-implement it here instead of re-using the code. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2020-07-22efi_loader: Rename and correct values for ARM_SMC_MM_*Ilias Apalodimas1-8/+8
Instead of adding the definition for the specific MM SVC used in StandAloneMM we added the one used in the standard SMC calls. So change the value from -4 to -5 to match the correct one defined in EDK2 and rename them to avoid future confusion Fixes 23a397d2e2fb: ("efi_loader: Add headers for EDK2 StandAloneMM communication") Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-20dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matchingDave Gerlach2-0/+146
Introduce UCLASS_SOC to be used for SOC identification and attribute matching based on the SoC ID info. This allows drivers to be provided for SoCs to retrieve SoC identifying information and also for matching device attributes for selecting SoC specific data. This is useful for other device drivers that may need different parameters or quirks enabled depending on the specific device variant in use. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20Revert "lib: fdt: Split fdtdec_setup_mem_size_base()"Michal Simek1-20/+0
This reverts commit 3ebe09d09a407f93022d945a205c5318239eb3f6. There is no user of this split function that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-20Revert "lib: fdt: Split fdtdec_setup_memory_banksize()"Michal Simek1-19/+0
This reverts commit 118f4d4559a4386fa87a1e2509e84a1986b24a34. There is no user of this split function that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-20cpu: Convert the methods to use a const udevice *Simon Glass1-8/+8
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-20mtd: spinand: micron: identify SPI NAND device with Continuous Read modeShivamurthy Shastri1-0/+1
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-20global_data: Add a generic global_data flag for SMP stateSimon Glass1-0/+1
Allow keeping track of whether all CPUs have been enabled yet. This allows us to know whether other CPUs need to be considered when updating CPU-specific settings such as MTRRs on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-18mips: octeon: Add minimal Octeon 3 EBB7304 EVK supportStefan Roese2-0/+39
This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board. Supported devices: - UART - reset - CFI parallel NOR flash Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-17include: pci_ids: Add Cavium devicesSuneel Garapati1-0/+18
Add VendorID and DeviceID for supported devices on OcteonTX/TX2 platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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