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path: root/include/fsl_ddr_sdram.h
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2017-04-12arm: freescale: Rename initdram() to fsl_initdram()Simon Glass1-0/+8
This function name shadows a global name but is in fact different. This is very confusing. Rename it to help with the following refactoring. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-18armv8/fsl_lsch2: Add chip power supply voltage setupHou Zhiqiang1-0/+1
Set up chip power supply voltage according to voltage ID. The fuse status register provides the values from on-chip voltage ID fuses programmed at the factory. These values define the voltage requirements for the chip. Main operations: 1. Set up the core voltage 2. Set up the SERDES voltage and reset SERDES lanes 3. Enable/disable DDR controller support 0.9V if needed Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-05fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu1-1/+2
- add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14driver/ddr/fsl: Add more debug registersYork Sun1-1/+1
32 more debug registers are added for newer DDR controllers. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-05-17driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu1-0/+4
The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu1-0/+3
Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu1-0/+4
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu1-1/+10
Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25driver/ddr/fsl: Add workaround for A009663Shengzhou Liu1-0/+1
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-19Add more SPDX-License-Identifier tagsTom Rini1-3/+1
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
2015-12-13driver/ddr/fsl: Update DDR4 RTT valuesYork Sun1-0/+9
DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun <yorksun@freescale.com>
2015-10-30drivers/ddr/fsl_ddr: Make SR_IE configurableJoakim Tjernlund1-0/+2
SR_IE(Self-refresh interrupt enable) is needed for Hardware Based Self-Refresh. Make it configurable and let board code handle the rest. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085aqds: Add support of LS2085AQDS platformYork Sun1-0/+1
The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2015-04-23driver/ddr/fsl: Add workaround for DDR erratum A008511York Sun1-0/+2
This erratum only applies to general purpose DDR controllers in LS2. It shouldn't be applied to DP-DDR controller. Check DDRC versoin number before applying workaround. Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-11fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian1-3/+9
With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-09-25driver/ddr/fsl: Fix tXP and tCKEYork Sun1-2/+0
The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25driver/ddr: Restruct driver to allow standalone memory spaceYork Sun1-4/+12
U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08driver/ddr/fsl: Add support of overriding chip select write levelingYork Sun1-0/+2
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22mpc85xx/t104x: Add deep sleep framework supportTang Yuantian1-0/+4
When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun1-7/+56
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21driver/ddr: Add 256 byte interleaving supportYork Sun1-0/+1
Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun1-0/+377
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
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