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2021-10-11sunxi: gpio: Remove bank-specific size macrosSamuel Holland1-2/+0
Since the beginning, all banks have had space for 32 pins, even when not all pins were implemented. Let's use a single constant for the GPIO bank size here, like the GPIO driver is already doing. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: gpio: Remove name_to_gpio macroSamuel Holland4-14/+14
This clarifies which callers must be updated to complete the DM_GPIO conversion. The only remaining caller of name_to_gpio in generic code is inside the !DM_GPIO block in cmd/gpio.c. DM_GPIO is always selected on sunxi, so that code cannot be reached. And after this commit, there are only two remaining implementations of name_to_gpio. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: Clean up inclusions of asm/arch/gpio.hSamuel Holland9-14/+2
As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11gpio: sunxi: Remove the sunxi_name_to_gpio_bank functionSamuel Holland1-14/+0
The only caller of this function was the MMC pinmux code, which used it to parse a string given from a Kconfig symbol. As the Kconfig symbol has been converted to a Boolean, this function is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11clk: sunxi: Move header out of arch directorySamuel Holland14-14/+14
The CCU header is only used by the DM drivers, not any platform code. Its current location adds an artificial dependency on CONFIG_ARM and ARCH_SUNXI, which will be problematic when adding the CCU driver for a RISC-V sunxi platform. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-09video: move MXS to KconfigAnatolij Gustschin2-4/+6
Move CONFIG_VIDEO_MXS from board headers to Kconfig and drop it from obsolete cfb_console driver. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-10-09video: remove not used mx3fb driverAnatolij Gustschin3-914/+0
i.MX31 support was removed, and the non dm-video driver is obsolete and not used. Remove it. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2021-10-09video: simplefb: Add 30bpp supportMark Kettenis1-1/+11
Recognize the canonical format strings for framebuffers in 30bpp mode and 32/24bpp mode. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-10-09video: Add 30bpp supportMark Kettenis1-3/+8
Add support for 30bpp mode where pixels are picked in 32-bit integers but use 10 bits instead of 8 bits for each component. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-10-08arm: a37xx: pci: Update private structure documentationMarek Behún1-8/+9
There were several changes for this structure but the documentation was not changed at the time. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: a37xx: pci: Cosmetic changeMarek Behún1-7/+7
Update indentation in driver's private structure. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root PortPali Rohár1-4/+22
Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, add support for handling and propagation of CRSSVE bit. When CRSSVE bit is unset (default), driver has to reissue config read/write request on CRS response. CRSSVE bit is supported only when CRSVIS bit is provided in read-only Root Capabilities register. So manually inject this CRSVIS bit into read response for that register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: a37xx: pci: Do not automatically enable bus mastering on PCI BridgePali Rohár1-6/+0
Now that PCI Bridge is working for the PCIe Root Port, U-Boot's PCI_PNP code automatically enables memory access and bus mastering when needed. We do not need to enable it when setting the HW up. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: a37xx: pci: Add support for accessing PCI Bridge on root busPali Rohár1-19/+124
Aardvark does not have a real PCIe Root Port device on the root bus. Instead it has PCIe registers of PCIe Root Port device mapped in internal Aardvark memory space starting at offset 0xc0. The PCIe Root Port itself is normally available as a PCI Bridge device on the root bus with bus number zero. Aardvark instead has the configuration registers of this PCI Bridge at offset 0x00 of Aardvark's memory space, but the class code of this device is Mass Storage Controller (0x010400), instead of PCI Bridge (0x600400), which causes U-Boot to fail to recognize it as a P2P Bridge Add a hook into the pcie_advk_read_config() / pcie_advk_write_config() functions to redirect access for root bus from PIO transfer to this internal Aardvark memory space. This will allow U-Boot to access configuration space of this PCI Bridge which represents PCIe Root Port. Redirect access to PCI Bridge registers in range 0x10 - 0x34 to driver's internal buffer (cfgcache[]). This is because at those addresses Aardvark has different registers, incompatible with config space of a PCI Bridge. Redirect access to PCI Bridge register PCI_ROM_ADDRESS1 (0x38) to Aardvark internal address for that register (0x30). When reading PCI Bridge register PCI_HEADER_TYPE, set it explicitly to value Type 1 (PCI_HEADER_TYPE_BRIDGE) as PCI Bridge must be of Type 1. When writing to PCI_PRIMARY_BUS or PCI_SECONDARY_BUS registers on this PCI Bridge, correctly update driver's first_busno and sec_busno variables, so that pcie_advk_addr_valid() function can check if address of any device behind the root bus is valid and that PIO transfers are started with correct config type (1 vs 0), which is required for accessing devices behind some PCI bridge after the root bus. U-Boot's PCI_PNP code sets primary and secondary bus numbers as relative to the configured bus number of the root bus. This is done so that U-Boot can support multiple PCIe host bridges or multiple root port buses, when internal bus numbers are different. Now that root bus is available, update code in pcie_advk_read_config() and pcie_advk_write_config() functions to correctly calculate real Aardvark bus number of the target device from U-Boot's bus number as: busno = PCI_BUS(bdf) - dev_seq(bus) Stefan: Small fix of header masking as suggested by Pali. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: a37xx: pci: Fix pcie_advk_link_up()Pali Rohár1-1/+2
Aardvark reports Disabled and Hot Reset LTSSM states as values >= 0x20. Link is not up in these states, so fix pcie_advk_link_up() function. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08phy: marvell: a3700: Return correct error code when power up failsPali Rohár1-6/+20
Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions may fail. In this case, do not continue execution of current function and instead jump to the end. Return value in 'ret' variable is already set. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08phy: marvell: a3700: Fix configuring polarity invert bitsPali Rohár1-0/+12
phy_txd_inv or phy_rxd_inv needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9406 Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initializationPali Rohár2-1/+2
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408 Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-07Merge tag 'u-boot-amlogic-20211007' of ↵Tom Rini2-7/+2
https://source.denx.de/u-boot/custodians/u-boot-amlogic - Add new SoC ID for S905Y2 found in Radxa Zero - pcie_dw_meson: fix usb fail when pci link fails to go up - Sync Amlogic DT from Linux 5.14 - dwc3-meson-gxl: add AXG compatible - dts: keep back HW order for MMC devices since change in Upstream Linux - Cleanup local AXG DT USB nodes now everything is upstream - distro_bootcmd: run pci enum for scsi_boot just like it is done for nvme_boot - New Boards: - Odroid-HC4: a variant of Odroid-C4 with 2 SATA ports (via PCIe-SATA bridge) - Beelink GS-King X: A variant of the other Beelink board with 2 SATA ports (via USB3-SATA bridge) - Banana Pi M5: another credit card SBC - JetHub D1/H1: home automation controllers - Radxa Zero: another RPi Zero sized SBC
2021-10-07usb: dwc3: meson-gxl: add AXG compatibleNeil Armstrong1-0/+1
Upstream Linux uses the "amlogic,meson-axg-usb-ctrl" for AXG SoCs. This adds it to the compatible list for this driver. Reported-by: Vyacheslav Bocharov <adeep@lexina.in> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Vyacheslav Bocharov <adeep@lexina.in>
2021-10-07pci: pcie_dw_meson: fix usb fail when pci link fails to go upNeil Armstrong1-7/+1
On Amlogic A311D, when the PCIe link fails disabling the related clocks makes USB fail. For an unknown reason, this doesn happen on the S905D3 SoC. Mimic the Linux behavior by not considering a link failure a probe failure, and continue even if the PCIe link is down. Reported-by: Art Nikpal <email2tema@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-07sysreset: provide SBI based sysreset driverHeinrich Schuchardt3-0/+64
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2021-10-07serial: Add a debug console using the RISC-V SBI interfaceSamuel Holland3-0/+27
The RISC-V SBI interface v0.1 provides a function for printing a character to the console. Even though SBI v0.1 functions are deprecated, the SBI console is quite useful for early debugging, because it works without any dcache, memory, or MMIO access in S mode. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-07clk: k210: Try harder to get the best configSean Anderson1-0/+24
In some cases, the best config cannot be used because the VCO would be out-of-spec. In these cases, we may need to try a worse combination of r/od in order to find the best representable config. This also adds a few test cases to catch this and other (possible) unlikely errors. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-07k210: clk: Refactor out_of_spec testsSean Anderson1-54/+53
Everything here sits in a while (true) loop. However, this introduces a couple of layers of indentation. We can simplify the code by introducing a single goto instead of using continue/break. This will also make adding loops in the next patch easier. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-07clk: k210: Fix checking if ulongs are less than 0Sean Anderson1-4/+5
The PLL functions take ulong arguments for rate, but still check if that rate is negative (which is never true). The correct way to handle this is to use IS_ERR_VALUE (like is already done in k210_clk_set_rate). While we're at it, we can move the error checking up into the caller of the pll set/get rate functions. This also protects our other calculations from using bogus values for rate. Fixes: 609bd60b94 ("clk: k210: Rewrite to remove CCF") Reported-by: Coverity Scan <scan-admin@coverity.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-06Convert CONFIG_NAND_OMAP_ECCSCHEME to KconfigTom Rini1-2/+101
The values of CONFIG_NAND_OMAP_ECCSCHEME map to the enum in include/linux/mtd/omap_gpmc.h for valid ECC schemes. Make which one we will use be a choice statement, enumerating the ones which we have implemented. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_NAND_FSL_ELBC et al to KconfigTom Rini1-0/+11
This converts the following to Kconfig: CONFIG_NAND_FSL_ELBC CONFIG_NAND_FSL_IFC Note that a number of PowerPC platforms had previously enabled CONFIG_NAND_FSL_ELBC without CONFIG_MTD_RAW_NAND, and now they no longer enable the option, reducing the size of a few functions. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_MAX_CHIPS to KconfigTom Rini2-7/+8
This converts the following to Kconfig: CONFIG_SYS_NAND_MAX_CHIPS Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06nand.h: Cleanup linux/mtd/rawnand.h usageTom Rini26-0/+26
We only include <linux/mtd/rawnand.h> in <nand.h> for the forward declaration of struct nand_chip, so do that directly. Then, include <linux/mtd/rawnand.h> where required directly. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_ONFI_DETECTION to KconfigTom Rini1-1/+8
This converts the following to Kconfig: CONFIG_SYS_NAND_ONFI_DETECTION Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_5_ADDR_CYCLE to KconfigTom Rini1-0/+9
This converts the following to Kconfig: CONFIG_SYS_NAND_5_ADDR_CYCLE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_BAD_BLOCK_POS to KconfigTom Rini1-0/+21
This converts the following to Kconfig: CONFIG_SYS_NAND_BAD_BLOCK_POS In order to do this, introduce a choice for HAS_LARGE/SMALL_BADBLOCK_POS as those are the only valid values. Use LARGE as the default as no in-tree boards use SMALL, but it is possible. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06nand_spl_simple: Drop CONFIG_SYS_NAND_4_ADDR_CYCLE supportTom Rini1-5/+0
This code is unused, drop it. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SYS_NAND_PAGE_COUNT to KconfigTom Rini1-0/+7
This converts the following to Kconfig: CONFIG_SYS_NAND_PAGE_COUNT Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_SPL_NAND_LOAD et al to KconfigTom Rini1-3/+14
This converts the following to Kconfig: CONFIG_SPL_NAND_LOAD CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_OOBSIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06Convert CONFIG_NAND_LPC32XX_MLC to KconfigTom Rini1-0/+5
This converts the following to Kconfig: CONFIG_NAND_LPC32XX_MLC Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-05reboot-mode: migrate uclass to livetreePatrick Delaunay1-14/+6
Use dev_ function to support a live tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05demo: migrate uclass to livetreePatrick Delaunay1-7/+2
Use dev_ function to read the sides and colour to support a live tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05remoteproc: migrate uclass to livetreePatrick Delaunay1-14/+2
Use dev_ function to read the name and boolean to support a live tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Factor out DT flag translationSamuel Holland1-21/+29
The generic GPIO flags binding is shared across many drivers, some of which need their own xlate function. Factor out the flag translation code from gpio_xlate_offs_flags so it does not need to be duplicated. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Verify validity of pin offsets from device treesSamuel Holland1-0/+4
Translation of an OF GPIO specifier should fail if the pin offset is larger than the number of pins in the GPIO bank. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05gpio: Verify validity of pin offsets when looking up namesSamuel Holland1-1/+2
Translation of a pin name to a device+offset should fail if the offset is larger than the number of pins in the GPIO bank. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05pinctrl: single: Add request() apiBharat Gooty1-0/+34
Add pinctrl_ops->request api to configure pctrl pad register in gpio mode. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-05pinctrl: single: Parse gpio details from dtBharat Gooty1-0/+52
Parse different gpio properties from dt as part of probe function. This detail is required to enable pinctrl pad later when gpio lines are requested. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
2021-10-04Merge branch 'next'Tom Rini313-3914/+2411
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-04mtd: cqspi: Fix division by zeroMarek Vasut1-0/+3
Both dummy.nbytes and dummy.buswidth may be zero. By not checking the later, it is possible to trigger division by zero and a crash. This does happen with tiny SPI NOR framework in SPL. Fix this by adding the check and returning zero dummy bytes in such a case. Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Pratyush Yadav <p.yadav@ti.com> [trini: Drop Pratyush's RB as his requested changes weren't made as Marek disagreed]
2021-10-03watchdog: rti_wdt: Add support for loading firmwareJan Kiszka2-0/+108
To avoid the need of extra boot scripting on AM65x for loading a watchdog firmware, add the required rproc init and loading logic for the first R5F core to the watchdog start handler. In case the R5F cluster is in lock-step mode, also initialize the second core. The firmware itself is embedded into U-Boot binary to ease access to it and ensure it is properly hashed in case of secure boot. One possible firmware source is https://github.com/siemens/k3-rti-wdt. The board is responsible for providing the firmware as additional loadable via the U-Boot fit image. The driver will pick up its location from /fit-images/k3-rti-wdt-firmware then. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-10-03pci: pcie_layerscape_fixup_common: lx2_board_fix_fdt can be staticVladimir Oltean1-1/+1
To avoid W=1 build warnings, declare this function as static, since it is not used outside of this translation module. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-03pci: pcie_layerscape_fixup_common: include fdt_support.h for ft_pci_setupVladimir Oltean1-0/+1
The function prototype for ft_pci_setup is inside fdt_support.h, we need to include that header. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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