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2014-12-11arm: ls102xa: Update PCIe dts node statusMinghuan Lian2-0/+52
The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-08Merge git://git.denx.de/u-boot-mpc85xxTom Rini12-15/+555
2014-12-08Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini8-35/+42
2014-12-08Merge git://git.denx.de/u-boot-i2cTom Rini1-4/+4
2014-12-08Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2-11/+16
2014-12-08blackfin: include <linux/compiler.h> rather than define __iomemMasahiro Yamada1-1/+0
The macro __iomem is defined in include/linux/compiler.h. Let's include it rather than double __iomem defines. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Sonic Zhang <sonic.adi@gmail.com>
2014-12-08Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada4-4/+4
Including <linux/compiler.h> is enough for general use. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08serial: pl01x: avoid pl01x type check two timesVikas Manocha1-9/+6
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08serial: pl01x: disable as per type of pl01xVikas Manocha1-3/+4
pl010 & pl011 have different control register offsets, setting it as per the pl01x type. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08serial: pl01x: move all line control at same placeVikas Manocha1-23/+21
Receive line control uses same setting as transmit line control, also one lcrh write is effective for both baud rate & receive line control internal update. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08serial: pl01x: fix pl011 baud rate configurationVikas Manocha1-0/+8
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which is updated on a single write strobe generated by a UART_LCR_H write. So, to internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H must always be performed at the end. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08serial: pl01x: pass pl01x_type to set baudrateVikas Manocha1-1/+1
Although we were checking the pl01x type, seems like PL010 type was being passed by mistake. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08i2c: Correct spelling errorMark Tomlinson1-3/+3
"diconnect" and "disconnet" should both be "disconnect". Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
2014-12-08i2c: Fix deselection of muxesMark Tomlinson1-1/+1
Due to an uninitialised variable, when muxes were deselected, any value could be written to the mux control register. On the PCA9548, this could result in multiple channels being selected, thus enabling multiple pull-up resistors, and much bus capacitance. The fix is simply to initialise the written value to zero. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
2014-12-05net/phy: enable serdes auto-negotiation for vsc8514 phyShengzhou Liu1-2/+11
VSC8514 QSGMII PHY requires enabling auto-negotiation, otherwise it wouldn't work. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05net/fman: update 10GEC to fit new SoCShengzhou Liu2-2/+7
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05powerpc/mpc85xx: Add T1024/T1023 SoC supportShengzhou Liu2-0/+90
Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05driver/ddr/fsl: Add workaround for faulty SPDYork Sun1-0/+22
Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39]. Using raw card spec in case this error is detected. Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfigSuresh Gupta1-2/+62
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp respectively in hwconfig. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05powerpc/b4860qds: add xfi supportShaohui Xie1-1/+3
We need following changes to make xfi work on B4: 1. set cross-point switch VSC3308 to use sfp config when running xfi; 2. add 10G interface check for xfi; 3. set phy address for xfi so the 10G ports can be registered by mdio; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05net/phy: Add support for CS4315/CS4340 PHYShengzhou Liu3-0/+337
Add support for Cortina CS4315/CS4340 10G PHY. - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device to initialize Cortina PHY. - Cortina PHY has non-standard offset of PHY ID registers, thus we define own get_phy_id() to override default get_phy_id(). - To define macro CONFIG_PHY_CORTINA will enable this driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slotsYork Sun1-6/+25
Increase write-to-write and read-to-read turnaround time for two-slot DDR configurations. Previously only quad-rank and two dual-rank configurations have this additional turnaround time. A recent test on two single-rank DIMMs shows the shorter additional turnaround time is also needed. Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05Freescale t104x: Do not exclude SGMIIJoakim Tjernlund1-4/+0
fman_port_enet_if() tests if FM1_DTSEC2 or FM1_DTSEC4 uses RGMII or MII and if not returns PHY_INTERFACE_MODE_NONE. This excludes testing for SGMII further down. Remove the unconditional "else return PHY_INTERFACE_MODE_NONE" so SGMII can be tested too. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-04ns16550.c: Fix for ns16550 driver hanging on OMAP4Gregoire Gentil1-4/+5
The same problem that is seen on some OMAP3 is also seen on some OMAP4 so include them in the test in order to prevent some hangs during SPL. [trini: Re-word commit message, make apply cleanly] Signed-off-by: Tom Rini <trini@ti.com>
2014-12-04mtd: nand: omap_gpmc: Always use ready/busy pinStefan Roese1-5/+4
The functions to detect the state of the ready / busy signal is already available but only used in the SPL case. Lets use it always, also for the main U-Boot. As all boards should have this HW connection. Testing on Siemens Draco (am335x) showed a small perfomance gain by using this ready pin to detect the NAND chip state. Here the values tested on Draco with Hynix 4GBit NAND: Without NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.947 seconds, 2947 ticks With NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.795 seconds, 2795 ticks So an increase of approx. 5%. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Samuel Egli <samuel.egli@siemens.com>
2014-12-04omap_hsmmc: Board-specific TWL4030 MMC power initializationsPaul Kocialkowski1-6/+1
Boards using the TWL4030 regulator may not all use the LDOs the same way (e.g. MMC2 power can be controlled by another LDO than VMMC2). This delegates TWL4030 MMC power initializations to board-specific functions, that may still call twl4030_power_mmc_init for the default behavior. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com> [trini: Fix omap3_evm warning, add twl4030.h] Signed-off-by: Tom Rini <trini@ti.com>
2014-12-05mmc: sh_mmcif: Add support rmobileNobuhiro Iwamatsu2-2/+7
Renesas R-Mobile/R-Car ARM SoC of MMC has the same IP that are supported by sh_mmcif. This adds support R-Mobile/R-Car ARM SoC with the setting of the clock support. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05mmc: sh_mmcif: Change maximum and minimum value of MMC clockNobuhiro Iwamatsu2-3/+5
Maximum value and the minimum value of clock for sh_mmcif instead by base of MMC clock. This removes fixed clock, make the changes to be calculated according to environment. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05mmc: sh_mmcif: Use DIV_ROUND_UP and fls instead of calculation loopNobuhiro Iwamatsu1-8/+6
Use DIV_ROUND_UP and fls to simplify the code. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-04twl4030: device-index-specific MMC power initializations, common ramp-up delayPaul Kocialkowski2-13/+19
Not every device has multiple MMC slots available, so it makes sense to enable only the required LDOs for the available slots. Generic code in omap_hsmmc will enable both VMMC1 and VMMC2, in doubt. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04mmc: Board-specific MMC power initializationsPaul Kocialkowski1-0/+7
Some devices may use non-standard combinations of regulators to power MMC: this allows these devices to provide a board-specific MMC power init function to set everything up in their own way. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04arm: omap: add support for am57xx devicesFelipe Balbi3-7/+8
just add a few ifdefs around because this device is very similar to dra7xxx. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04usb: phy: omap_usb_phy: fix build breakageFelipe Balbi1-2/+0
there's no such function usb3_phy_power(), it's likely that author meant to call, usb_phy_power() instead, but that's already called properly from xhci-omap.c. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2014-12-01Merge git://git.denx.de/u-boot-fdtTom Rini1-1/+1
2014-12-01Merge git://git.denx.de/u-boot-x86Tom Rini22-213/+665
2014-11-27Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2-9/+48
2014-11-28usb: UniPhier: support OF configurationMasahiro Yamada1-1/+37
If CONFIG_OF_CONTROL is defined, search device tree nodes that are compatible with "panasonic,uniphier-ehci" and take the base address from their "reg" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de>
2014-11-28serial: UniPhier: support OF configurationMasahiro Yamada1-8/+11
This commit implements the ofdata_to_platdata handler for the UniPhier serial driver and adds serial device nodes to the device tree sources. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-27fdt: remove fdtdec_get_alias_node() functionMasahiro Yamada1-1/+1
The fdt_path_offset() checks an alias too. fdtdec_get_alias_node(blob, "foo") is equivalent to fdt_path_offset(blob, "foo"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-11-26mtd: nand: s3c: Unify the register definition and namingMarek Vasut1-19/+19
Merge struct s3c2410_nand and struct s3c2440_nand into one unified struct s3c24x0_nand. While at it, fix up and rename the functions to retrieve the NAND base address and fix up the s3c NAND driver to reflect this change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Vladimir Zapolskiy <vz@mleia.com>
2014-11-26mtd/nand/vf610_nfc: Disable subpage writesSanchayan Maity1-0/+3
This patch disables subpage writes for vf610_nfc nand driver. This is required, as without this fix, writing unaligned u-boot images with DFU results in a hang. Trying to write unalgined binary images also results in a hang, without disabling subpage writes. Patch has been tested on a Colibri VF61 module. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
2014-11-26mtd: denali: set some registers after nand_scan_ident()Masahiro Yamada1-0/+11
Some but not all of implementations of the Denali NAND controller have hardware circuits to detect the device parameters such as page_size, erase_size, etc. Even on those SoCs with such hardware supported, the hardware is known to detect wrong parameters for some nasty (almost buggy) NAND devices. The device parameters detected during nand_scan_ident() are more trustworthy. This commit sets some hardware registers to mtd->pagesize, mtd->oobsize, etc. in the code between nand_scan_ident() and nand_scan_tail(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Chin Liang See <clsee@altera.com>
2014-11-26mtd: denali: use CONFIG_SYS_NAND_SELF_INITMasahiro Yamada3-40/+93
Some variants of the Denali NAND controller need some registers set up based on the device information that has been detected during nand_scan_ident(). CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between nand_scan_ident() and nand_scan_tail(). It is also helpful to reduce the difference between this driver and its Linux counterpart because this driver was ported from Linux. Moreover, doc/README.nand recommends to use CONFIG_SYS_NAND_SELF_INIT. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Chin Liang See <clsee@altera.com>
2014-11-26nand: reinstate lazy bad block scanningRostislav Lisovy1-3/+7
Commit ff94bc40af3481d47546595ba73c136de6af6929 ("mtd, ubi, ubifs: resync with Linux-3.14") accidentally reverted part of the commit 13f0fd94e3cae6f8a0d9fba5d367e311edc8ebde ("NAND: Scan bad blocks lazily."). Reinstate the change as by commit fb49454b1b6c7c6e238ac3c0b1e302e73eb1a1ea ("nand: reinstate lazy bad block scanning") Signed-off-by: Rostislav Lisovy <lisovy@merica.cz> Acked-by: Heiko Schocher <hs@denx.de>
2014-11-26Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini6-4/+152
2014-11-26Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2-5/+13
Conflicts: drivers/mmc/fsl_esdhc.c Signed-off-by: Tom Rini <trini@ti.com>
2014-11-26Merge branch 'master' of http://git.denx.de/u-boot-samsungTom Rini2-11/+96
2014-11-25bios_emulator: Always print errors when opcode decode failsSimon Glass3-18/+22
This is a rare event and should not happen. When it does it is confusing to work out why. At least we should print a message. Adjust the emulator to always print decode errors to the console. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25bios_emulator: Add an option to enable debuggingSimon Glass9-54/+90
At present there are DEBUG options spread around the place. If you enable one and not another you can end up with an emulator that does not work, since each file can have a different view of what the registers look like. To fix this, create a global CONFIG_X86EMU_DEBUG option that keeps everything consistent. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25bios_emulator: Allow a custom interrupt handler to be installedSimon Glass2-0/+6
Sometime we want to provide an interrupt handler for the ROM, Add a function to allow this. Signed-off-by: Simon Glass <sjg@chromium.org>
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