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2021-10-31pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoCDzmitry Sankouski2-3/+6
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephan Gerhold <stephan@gerhold.net> [trini: Add CONFIG_SDM845 around sdm845_data usage]
2021-10-31spmi: msm: add arbiter version 5 supportDzmitry Sankouski1-50/+104
Currently driver supports only version 1 and 2. Version 5 has slightly different registers structure Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2021-10-31serial: qcom: add support for GENI serial driverDzmitry Sankouski3-0/+632
Generic Interface (GENI) Serial Engine (SE) based uart can be found on newer qualcomm SOCs, starting from SDM845. Tested on Samsung SM-G9600(starqltechn) by chain-loading u-boot with stock bootloader. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2021-10-31iommu: Add Apple DART driverMark Kettenis3-0/+70
The DART is an IOMMU that is used on Apple's M1 SoC. This driver configures the DART such that it operates in bypass mode which is enough to support DMA for the USB3 ports integrated on the SoC. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31serial: s5p: Add Apple M1 supportMark Kettenis2-24/+84
Apple M1 SoCs include an S5L UART which is a variant of the S5P UART. Add support for this variant and enable it by default on Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31test: Add tests for IOMMU uclassMark Kettenis2-0/+20
Add a set of tests for the IOMMU uclass. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31iommu: Add IOMMU uclassMark Kettenis6-0/+76
This uclass is intended to manage IOMMUs on systems where the IOMMUs are not in bypass mode by default. In that case U-Boot cannot ignore the IOMMUs if it wants to use devices that need to do DMA and sit behind such an IOMMU. This initial IOMMU uclass implementation does not implement and device ops and is intended for IOMMUs that have a bypass mode that does not require address translation. Support for IOMMUs that do require address translation is planned and device ops will be defined when support for such IOMMUs will be added. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-29mmc: arm_pl180_mmci: Enable HWFC for specific versions of MCIUsama Arif2-0/+15
There are 4 registers (PERIPHID{0-3}) that contain the ID of MCI. For MMCs' with peripheral id 0x02041180 and 0x03041180, H/W flow control needs to be enabled for multi block writes (MMC CMD 18). Signed-off-by: Usama Arif <usama.arif@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29mmc: Fix mmc_switch excessive timeoutKirill Kapranov1-2/+2
Fix branching to avoid premature falling back on a long timeout instead of continuation of the initialization attempt. Clear of the comment to avoid the ambiguity. Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Marek Behún <marek.behun@nic.cz> Tested-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29drivers: mmc: Add wait_dat0 support for sdhci driverStephen Carlson1-0/+20
Adds an implementation of the wait_dat0 MMC operation for the DM SDHCI driver, allowing the driver to continue when the card is ready rather than waiting for the worst case time on each MMC switch operation. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-29drivers: mmc: Add wait_dat0 support for Freescale eSDHC driverStephen Carlson1-0/+16
Adds an implementation of the wait_dat0 MMC operation for the Freescale eSHDC driver, allowing the driver to continue when the card is ready rather than waiting for the worst case time on each MMC switch operation. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-26dfu: Sort Kconfig entries alphabeticallyMarek Vasut1-7/+7
The DFU_MTD Kconfig entry is in the wrong position, move it into the correct alphabetically sorted position. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-10-25dfu: dfu_sf: Read the SPI flash in 16 MiB chunksMarek Vasut1-2/+12
Not all SPI flashes and controllers can do continuous transfer longer than 16 MiB, so perform the DFU read in 16 MiB chunks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2021-10-25mmc: sunxi: conditionally include MMC2 initialization codeIcenowy Zheng1-0/+2
Allwinner R329 has no MMC2. Only include the code of MMC2 if the base address of it is defined. Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25watchdog: Add a driver for the sunxi watchdogSamuel Holland3-0/+197
This driver supports the sun4i/sun6i/sun20i watchdog timers. They have a maximum timeout of 16 seconds. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25clk: sunxi: Extend DM_RESET selection to SPLSamuel Holland1-0/+1
The sunxi clock driver exposes a reset controller, so it selects the reset controller framework. Ensure that dependency is also satisfied when building the driver for the SPL. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25power: pmic: axp: Implement poweroff via sysresetSamuel Holland2-1/+50
The AXP PMICs have the ability to power off the system. The existing code for this is duplicated for each PMIC variant, and uses the legacy non-DM "pmic_bus" interface. When SYSRESET is enabled, this can all be replaced with a sysreset device using the DM_PMIC interface. Since the trigger bit is the same on all PMIC variants, use the register definitions from the oldest supported PMIC. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25power: axp: Avoid do_poweroff conflict with sysresetSamuel Holland6-1/+11
The sysreset uclass has an option to provide the do_poweroff() function. When that option is enabled, the AXP power drivers should not provide their own definition. For the AXP305, which is paired with 64-bit systems where TF-A provides PSCI, there is another possible conflict with the PSCI firmware driver. This driver can be enabled even if CONFIG_PSCI_RESET is disabled, so make sure to use the right symbol in the condition. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Support VBUS detection via power supplySamuel Holland2-0/+8
The device tree binding provides for getting VBUS state from a device referenced by phandle, as an optional alternative to using a GPIO. In U-Boot, where there is no power supply class, this VBUS detection will be implemented using a regulator device and its get_enable method. Let's hook this up to the PHY driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Refactor VBUS detection to match LinuxSamuel Holland1-13/+12
The Linux driver checks the VBUS detection GPIO first; then VBUS power supply; then finally assumes VBUS is present. When adding VBUS power supply support, we want to match that order, so we get the same behavior in case both a GPIO and a power supply are provided in the device tree. So refactor the function a bit to remove the early return, and use the same "assume VBUS is present" final fallback. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Remove a couple of debug messagesSamuel Holland1-4/+0
Both of these messages log the GPIO number of the ID detection GPIO, which is not terribly useful, especially in the VBUS detection function. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-23Merge https://source.denx.de/u-boot/custodians/u-boot-spiTom Rini13-85/+147
- Fix mtd erase with mtdpart (Marek Behún) - NXP fspi driver fixes (Kuldeep Singh)
2021-10-23spi: nxp_fspi: Implement errata workaround for LS1028AKuldeep Singh1-5/+48
Errata ERR050568 description says that "Flash access by FlexSPI AHB command may not work with platform frequency equal to 300 MHz" on LS1028A. By default, smaller length reads(equal to RX FIFO size) are done by IP bus and larger length reads using AHB bus. For adding errata workaround, use IP bus to read entire flash contents and disable AHB path when platform frequency is 300Mhz. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23spi: nxp-fspi: Add support for IP read onlyKuldeep Singh1-4/+20
Add support for disabling AHB bus and read entire flash contents via IP bus only. Please note, this enables IP bus read using a quirk which can be enabled directly in device-type data or in existence of an errata where AHB bus may need to be disabled. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: spi-nor-ids: Add SECT_4K to mt25qu512aKris Chaplin1-1/+1
The mt25qu512a supports 4K or 64K sectors, so adding SECT_4K to enable 4K sector usage. Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> [jagan: droped Tested-by of patch author and datasheet link] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: spi-nor-ids: Add is25lp512 and is25wp512 devicesKris Chaplin1-0/+4
Add is25lp512 and is25wp512 devices to spi-nor id table Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> [jagan: droped Tested-by of patch author] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: Remove mtd_erase_callback() entirelyMarek Behún10-68/+2
The original purpose of mtd_erase_callback() in Linux at the time it was imported to U-Boot, was to inform the caller that erasing is done (since it was an asynchronous operation). All supplied callback methods in U-Boot do nothing, but the mtd_erase_callback() function was (until previous patch) grossly abused in U-Boot's mtdpart implementation for completely different purpose. Since we got rid of the abusement, remove the mtd_erase_callback() function and the .callback member from struct erase_info entirely, in order to avoid such problems in the future. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-23mtd: mtdpart: Make mtdpart's _erase method saneMarek Behún1-8/+18
The _erase() method of the mtdpart driver, part_erase(), currently implements offset shifting (for given mtdpart partition) in a weird way: 1. part_erase() adds partition offset to block address 2. parent driver's _erase() method is called 3. parent driver's _erase() method calls mtd_erase_callback() 4. mtd_erase_callback() subtracts partition offset from block address so that the callback function is given correct address The problem here is that if the parent's driver does not call mtd_erase_callback() in some scenario (this was recently a case for spi_nor_erase(), which did not call mtd_erase_callback() at all), the offset is not shifted back. Moreover the code would be more readable if part_erase() not only added partition offset before calling parent's _erase(), but also subtracted it back afterwards. Currently the mtd_erase_callback() is expected to do this subtracting since it does have to do it anyway. Add the more steps to this procedure: 5. mtd_erase_callback() adds partition offset to block address so that it returns the the erase_info structure members as it received them 6. part_erase() subtracts partition offset from block address This makes the code more logical and also prevents errors in case parent's driver does not call mtd_erase_callback() for some reason. (BTW, the purpose of mtd_erase_callback() in Linux is to inform the caller that it is done, since in Linux erasing is done asynchronously. We are abusing the purpose of mtd_erase_callback() in U-Boot for completely different purpose. The callback function itself has empty implementation in all cases in U-Boot.) Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Check for ctrlc() in spi_nor_erase()Marek Behún1-0/+5
May it possible to interrupt the spi_nor_erase() function. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Call mtd_erase_callback() from spi_nor_erase()Marek Behún1-2/+18
The spi_nor_erase() function does not call mtd_erase_callback() as it should. The mtdpart code currently implements the subtraction of partition offset in mtd_erase_callback(). This results in partition offset being added prior calling spi_nor_erase(), but not subtracted back on return. The result is that the `mtd erase` command does not erase the whole partition, only some of it's blocks: => mtd erase "Rescue system" Erasing 0x00000000 ... 0x006fffff (1792 eraseblock(s)) jedec_spi_nor spi-nor@0: at 0x100000, len 4096 jedec_spi_nor spi-nor@0: at 0x201000, len 4096 jedec_spi_nor spi-nor@0: at 0x302000, len 4096 jedec_spi_nor spi-nor@0: at 0x403000, len 4096 jedec_spi_nor spi-nor@0: at 0x504000, len 4096 jedec_spi_nor spi-nor@0: at 0x605000, len 4096 jedec_spi_nor spi-nor@0: at 0x706000, len 4096 This is obviously wrong. Add proper calling of mtd_erase_callback() into the spi_nor_erase() function. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Don't check for zero length in spi_nor_write() / ↵Marek Behún1-6/+0
spi_nor_erase() This check is already done in all callers: mtdcore's mtd_write() / mtd_erase(), legacy spi_nor_write() / spi_flash_erase(). No reason to do this here as well. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-23mtd: spi-nor-core: Check return value of write_disable() in spi_nor_erase()Marek Behún1-1/+3
The cleanup code of spi_nor_erase() function calls write_disable(), but does not return it's return value even in case of failure. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Don't overwrite return value if it is non-zeroMarek Behún1-2/+4
The cleanup code of the spi_nor_erase() function overwrites the ret variable with return value of clean_bar(), even if the ret variable is already set. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Check return value of write_enable() in spi_nor_erase()Marek Behún1-1/+3
The spi_nor_erase() function does not check return value of the write_enable() call. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Try cleaning up in case writing BAR failedMarek Behún1-1/+1
Use the cleanup codepath of spi_nor_erase() also in the event of failure of writing the BAR register. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor: Add support for Spansion S25FL256LTakahiro Kuwano2-0/+20
The S25FL256L is a part of the S25FL-L family and has the same feature set as S25FL128L except the density. The datasheet can be found in the following link. https://www.cypress.com/file/316171/download The S25FL256L is 32MB NOR Flash that does not support Bank Address Register. This fixup is activated if CONFIG_SPI_FLASH_BAR is enabled and returns ENOTSUPP in setup() hook to avoid further ops. Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
2021-10-23mtd: spi-nor-ids: Add GD25LQ256D ChipYanhong Wang1-0/+5
Add Gigadevice GD25LQ256D SPI NOR chip. https://www.gigadevice.com/datasheet/gd25lq256d/ Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [jagan: updated commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-21Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini3-2/+12
- Turris MOX and Omnia changes, mostly moving to Kconfig (Marek) - a37xx: pci: Misc smaller fixes (Pali) - cmd: tlv_eeprom: Fix building with DEBUG enabled (Sven) - termios_linux.h: Fix tcsendbreak() implementation (Pali) - mvebu: Add missing "if SPL" (Tom)
2021-10-21arm: a37xx: pci: Fix condition for CRS responsePali Rohár1-1/+1
As stated in comment above the code, CRS response can be returned to OS only for 4-byte PCI_VENDOR_ID config read request. So fix the code. Fixes: 1d7ad68559e2 ("arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-21arm: a37xx: pci: Do not allow setting bars on PCI BridgePali Rohár1-0/+4
PCI Bridge which represents Aardvark PCIe Root Port does not have configurable bars. So ensure that write operation to bars registers on PCI Bridge is noop and bars registers always contain zero address which indicates that bars are unsupported. After this change U-Boot 'pci bar 0.0.0' command does not show any allocated bars for PCI Bridge device. Signed-off-by: Pali Rohár <pali@kernel.org> Fixes: cb056005dc67 ("arm: a37xx: pci: Add support for accessing PCI Bridge on root bus") Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-21arm: mvebu: a3720: Create Kconfig option for I2C_MVMarek Behún2-1/+7
Move the config option CONFIG_I2C_MV to a Kconfig option CONFIG_SYS_I2C_MV and move the default definition from config header files into defconfigs. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-20Merge tag 'u-boot-imx-20211020' of ↵Tom Rini6-6/+32
https://source.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20211020 ------------------- First PR from u-boot-imx for 2022.01 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535 - new board: kontron-sl-mx8mm - imx8m: - fix secure boot - imx ESDHC: fixes - i.MX53: Support thum2, bmode and fixes for Menlo board usbarmory switch to Ethernet driver model - imx6 : - DDR calibration for Toradex boards - imx7: - Fixes - Updated gateworks boards (ventana / venice) # gpg verification failed.
2021-10-20ram: sifive: Fix -Wint-to-pointer-cast warningsBin Meng1-4/+4
The following warning is seen in sifive_ddr.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_index_ptr(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-20net: macb: Fix -Wint-to-pointer-cast warningsBin Meng1-8/+3
The following warning is seen in macb.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_index_ptr(), or cast with uintptr_t. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-10-20dm: core: Add a new API devfdt_get_addr_index_ptr()Bin Meng1-3/+8
At present there is only devfdt_get_addr_ptr() which only returns the first <addr, size> pair in the 'reg' property. Add a new API devfdt_get_addr_index_ptr() to return the indexed pointer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-20i2c: ocores: Fix -Wint-to-pointer-cast warningBin Meng1-1/+1
The following warning is seen in ocores_i2c.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-20gpio: sifive: Fix -Wint-to-pointer-cast warningBin Meng1-4/+2
dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit address and plat->base is a pointer. In a 32-bit build, this causes the following warning seen when building sifive-gpio.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-20clk: sifive: Fix -Wint-to-pointer-cast warningBin Meng1-3/+3
dev_read_addr() returns a value of type fdt_addr_t which is a 64-bit address and pd->va is a pointer. In a 32-bit build, this causes the following warning seen when building sifive-prci.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Change to use dev_read_addr_ptr(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-20cache: sifive: Fix -Wint-to-pointer-cast warningBin Meng1-1/+1
The following warning is seen in cache-sifive-ccache.c in a 32-bit build: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Fix by casting it with uintptr_t. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-19clk: fixed_rate: add dummy disable() functionSamuel Holland1-0/+1
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function") implemented .enable, so fixed rate clocks can be used where drivers might call clk_enable(). Implement the .disable op for the same reason; some drivers, e.g. USB PHYs, may attempt to disable clocks at runtime. Signed-off-by: Samuel Holland <samuel@sholland.org>
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