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2022-12-05global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini68-499/+499
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini28-94/+94
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*Tom Rini7-36/+36
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05rtc: Remove unused driversTom Rini4-525/+0
These RTC drivers are currently unused and reference other unused CONFIG variables, so remove them. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_*Tom Rini5-31/+31
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_*Tom Rini5-60/+60
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SYS_NS16550_MEM32 et al to KconfigTom Rini2-9/+47
This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-05powerpc: Rename CONFIG_NS16550_MIN_FUNCTIONSTom Rini2-6/+6
This symbol is specific to the PowerPC SPL implementation, so rename this to reflect that it's in SPL and used / tested there, so that we can then safely migrate it to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_*Tom Rini18-94/+94
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SYS_NAND_SIZE to KconfigTom Rini1-0/+5
This converts the following to Kconfig: CONFIG_SYS_NAND_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SYS_NAND_PAGE_2K et al to KconfigTom Rini1-0/+13
This converts the following to Kconfig: CONFIG_SYS_NAND_PAGE_2K CONFIG_SYS_NAND_PAGE_4K Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE to KconfigTom Rini1-0/+4
This converts the following to Kconfig: CONFIG_SYS_NAND_NO_SUBPAGE_WRITE Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to KconfigTom Rini1-0/+18
This converts the following to Kconfig: CONFIG_SYS_NAND_MAX_OOBFREE CONFIG_SYS_NAND_MAX_ECCPOS Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directlyTom Rini1-9/+9
This is the only driver, and only one platform makes use of, setting CONFIG_SYS_NAND_ECC_BASE. Reference ATMEL_BASE_ECC directly in this case. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SYS_NAND_HW_ECC to KconfigTom Rini2-5/+16
This converts the following to Kconfig: CONFIG_SYS_NAND_HW_ECC Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to KconfigTom Rini1-0/+5
This converts the following to Kconfig: CONFIG_SYS_NAND_HW_ECC_OOBFIRST Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Convert CONFIG_SYS_NAND_DBW_8 et al to KconfigTom Rini1-0/+12
This converts the following to Kconfig: CONFIG_SYS_NAND_DBW_8 CONFIG_SYS_NAND_DBW_16 Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16 being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of the configs set CONFIG_SYS_NAND_DBW_8. So we introduce CONFIG_SYS_NAND_DBW_16 as an option. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05Merge tag 'xilinx-for-v2023.01-rc3-v2' of ↵Tom Rini4-11/+75
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.01-rc3-v2 xilinx: - Fix MAC address selection for System Controller from FRU - Cleanup Kconfig (ZYNQ_MAC_IN_EEPROM symbol) versal: - Create u-boot.elf for mini spi configurations versal-net: - Enable MT35XU flash zynq: - Add missing timer to DT for mini configurations zynqmp: - Do not include psu_init to U-Boot by default - Do not enable IPI by default to mini U-Boot - Update Luca's fragment - Fix SPL_FS_LOAD_PAYLOAD_NAME usage spi: - gqspi: Fix tapdelay values - gqspi: Fix 64bit address support - cadence: Remove condition for calling enable linear mode - nor-core: Invert logic to reflect sst26 flash unlocked net: - Add PCS/PMA phy support
2022-12-05mtd: spi-nor-core: Invert logic to reflect sst26 flash unlockedAlgapally Santosh Sagar1-1/+1
flash_is_locked is changed to flash_is_unlocked with commit 513c6071ce73 ("mtd: spi: Convert is_locked callback to is_unlocked"). sst26_is_locked() is also changed to sst26_is_unlocked() but the logic remained same. Invert the logic for the flash lock/unlock to work properly. Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20221122051833.13306-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05spi: cadence-qspi: Remove condition for calling enable linear modeAshok Reddy Soma1-5/+1
cadence_qspi_apb_enable_linear_mode() has a weak function defined, so no need to gaurd this under if (CONFIG_IS_ENABLED(ARCH_VERSAL)). In cadence_qspi_apb_write_execute(), enable linear mode is called twice by mistake, remove extra one. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20221129114134.18909-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05spi: zynqmp_qspi: Add support for 64-bit read/writeVenkatesh Yadav Abbarapu1-2/+4
When we pass the 64-bit address to read/write, only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register, which can handle upto 44-bit destination address. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20221125104413.26140-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05spi: zynqmp_gqspi: Update tapdelay valueT Karthik Reddy1-1/+1
The driver was using an incorrect value for GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay for Versal for frequencies above 100MHz. Change it from 2 to 1 based on the recommended value in IP spec. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20221123090451.11409-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05net: xilinx_axi: check PCS/PMA PHY status in setup_phyAndy Chiu1-0/+44
Both PCS/PMA PHY and the external PHY need to have a valid link status in order to have Ethernet traffic. Check and wait this status at setup_phy() so that we could diagnose if there is a PHY issue. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Link: https://lore.kernel.org/r/20221101035800.912644-3-andy.chiu@sifive.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05net: xilinx_axi: add PCS/PMA PHYAndy Chiu1-2/+24
If we bridge an external PHY to Xilinx's PCS/PMA PHY and would like to get and set the real status of the PHY facing the external world. Then we should phy_connect() to the external PHY instead of the PCS/PMA one. Thus, we add a pcs-handle DT entry, which have been merged in Linux, and leave the configuration of it to the driver itself. Unlike Linux, where the PCS/PMA PHY is managed by phylink, managing the PCS/PMA PHY is only internal to the driver in U-Boot. The PCS/PMA PHY pressents only when the phy-mode is configured as SGMII or 1000Base-X, so it is always 1 Gbps and full-duplex and we may skip passing link information out. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Link: https://lore.kernel.org/r/20221101035800.912644-2-andy.chiu@sifive.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-05i2c: nuvoton: renamed the NPCM i2c driverJim Liu1-0/+0
The Makefile name is npcm_i2c but the driver is npcm-i2c. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2022-12-02bus: Optionally include TI sysc driver in SPL/TPLPaul Barker3-2/+12
The TI sysc bus driver is required to allow access to the SPI bus on am335x platforms. To support SPI boot this driver needs to be enabled in the SPL/TPL as appropriate. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02bus: TI sysc driver requires DMPaul Barker1-1/+1
This driver does not build if CONFIG_DM is disabled as it uses the function `dev_get_priv`. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-12-02dm: core: Fix iteration over driver_info recordsPaul Barker1-3/+3
We should only perform additional iteration steps when needed to initialize the parent of a device. Other binding errors (such as a missing driver) should not lead to additional iteration steps. Unnecessary iteration steps can cause issues when memory is tightly constrained (such as in the TPL/SPL) since device_bind_by_name() unconditionally allocates memory for a struct udevice. On the SanCloud BBE this led to boot failure caused by memory exhaustion in the SPL when booting from SPI flash. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2022-11-28phy: add driver for Intel XWAY PHYTim Harvey4-0/+57
Add a driver for the Intel XWAY GbE PHY: - configure RGMII using dt phy-mode and standard delay properties - use genphy_config Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-11-28net: macb: Fix race caused by flushing unwanted descriptorsYaron Micher1-12/+39
The rx descriptor list is in cached memory, and there may be multiple descriptors per cache-line. After reclaim_rx_buffers marks a descriptor as unused it does a cache flush, which causes the entire cache-line to be written to memory, which may override other descriptors in the same cache-line that the controller may have written to. The fix skips freeing descriptors that are not the last in a cache-line, and if the freed descriptor is the last one in a cache-line, it marks all the descriptors in the cache-line as unused. This is similarly to what is done in drivers/net/fec_mxc.c In my case this bug caused tftpboot to fail some times when other packets are sent to u-boot in addition to the ongoing tftp (e.g. ping). The driver would stop receiving new packets because it is waiting on a descriptor that is marked unused, when in reality the descriptor contains a new unprocessed packet but while freeing the previous buffer descriptor & flushing the cache, the driver accidentally marked the descriptor as unused. Signed-off-by: Yaron Micher <yaronm@hailo.ai>
2022-11-28drivers: net: aquantia: fix typosTim Harvey1-4/+4
Fix a couple of typos: - s/Acquantia/Aquantia/ - s/firmare/firmware/ Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28net: dwc_eth_qos: Add support for bulk RX descriptor cleaningMarek Vasut2-23/+46
Add new desc_per_cacheline property which lets a platform run RX descriptor cleanup after every power-of-2 - 1 received packets instead of every packet. This is useful on platforms where (axi_bus_width EQOS_AXI_WIDTH_n * DMA DSL inter-descriptor word skip count + DMA descriptor size) is less than cache line size, which necessitates packing multiple DMA descriptors into single cache line. In case of TX descriptors, this is not a problem, since the driver always does synchronous TX, i.e. the TX descriptor is always written, flushed and polled for completion in eqos_send(). In case of RX descriptors, it is necessary to update their status in bulk, i.e. after the entire cache line worth of RX descriptors has been used up to receive data. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28net: dwc_eth_qos: Split TX and RX DMA ringsMarek Vasut2-12/+24
Separate TX and RX DMA rings to make their handling slightly clearer. This is a preparatory patch for bulk RX descriptor flushing. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-28liteeth: LiteX Ethernet deviceJoel Stanley3-0/+220
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-11-27usb: dwc3: Drop support for "snps, ref-clock-period-ns" DT propertyMarek Vasut1-4/+0
Drop support for quickly deprecated DT property "snps,ref-clock-period-ns" to prevent its proliferation. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-27usb: dwc3: Program GFLADJSean Anderson2-0/+44
GUCTL.REFCLKPER can only account for clock frequencies with integer periods. To address this, program REFCLK_FLADJ with the relative error caused by period truncation. The formula given in the register reference has been rearranged to allow calculation based on rate (instead of period), and to allow for fixed-point arithmetic. Additionally, calculate a value for 240MHZDECR. This configures a simulated 240Mhz clock using a counter with one fractional bit (PLS1). This register is programmed only for versions >= 2.50a, since this is the check also used by commit db2be4e9e30c ("usb: dwc3: Add frame length adjustment quirk"). [ marek: Ported from Linux kernel commit 596c87856e08d ("usb: dwc3: Program GFLADJ") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: Calculate REFCLKPER based on reference clockSean Anderson1-2/+13
Instead of using a special property to determine the reference clock period, use the rate of the reference clock. When we have a legacy snps,ref-clock-period-ns property and no reference clock, use it instead. Fractional clocks are not currently supported, and will be dealt with in the next commit. [ marek: Ported from Linux kernel commit 5114c3ee24875 ("usb: dwc3: Calculate REFCLKPER based on reference clock") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: reference clock period configurationBalaji Prakash J2-0/+33
Set reference clock period when it differs from dwc3 default hardware set. We could calculate clock period based on reference clock frequency. But this information is not always available. This is the case of PCI bus attached USB host. For that reason we use a custom property. Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference clock while hardware default is 19.2 MHz. [ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from property name; mention tested hardware ] [ marek: Ported from Linux kernel commit 7bee318838890 ("usb: dwc3: reference clock period configuration") ] Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Marek Vasut <marex@denx.de> # Port from Linux
2022-11-27usb: dwc3: Cache ref_clk pointer in struct dwc3Marek Vasut2-0/+12
Cache ref_clk clock pointer in struct dwc3 . This is a preparatory patch for subsequent backports from Linux kernel which configure GFLADJ register content based on the ref_clk rate and therefore need access to the ref_clk pointer. It is possible to extract the clock pointer from existing clk_bulk list of already claimed clock, no need to call clk_get*() again. Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2022-11-27usb: Expand buffer size in usb_find_and_bind_driver()Marek Vasut1-1/+1
The "generic_bus_%x_dev_%x" string which is printed into this buffer can be up to 34 characters long ("generic_bus_12345678_dev_12345678"). The buffer would be clipped by snprintf() if both %x were at maximum range. Make sure the buffer is long enough to cover such possibility. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-24ram: ast2600: Align the RL and WL settingDylan Hung1-0/+9
Use macro to represent the RL and WL setting to ensure the PHY and controller setting are aligned. Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24ram: ast2600: Improve ddr4 timing and signal qualityDylan Hung1-25/+138
Adjust the following settings to get better timing and signal quality. 1. write DQS/DQ delay - 1e6e2304[0] - 1e6e2304[15:8] 2. read DQS/DQ delay - 0x1e6e0298[0] - 0x1e6e0298[15:8] 3. CLK/CA timing - 0x1e6e01a8[31] 4. Read and write termination - change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8]) - change RTT_PARK from disable to 48 ohm (MR5[8:6]) - change RTT_WR from 120 ohm to disable (MR2[11:9]) - change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8]) Note1: Both DDR-PHY and DDR controller have their own registers for DDR4 Mode Registers (MR0~MR6). This patch introduces macros to synchronize the MR value on both sides. Note2: the waveform meansurement can be found in item #21 of Aspeed AST26x0 Application note (AP note). Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-24ram: ast2600: Fix incorrect statement of the register pollingDylan Hung1-6/+1
The condition "~data" in the if-statement is a typo. The original intention is to poll if SDRAM_PHYCTRL0_INIT bit equals to 0. So use "data == 0" for instead. Besides, the bit[1] of "phy_status" register is hardwired to SDRAM_PHYCTRL0_INIT (with inverse logic). Since SDRAM_PHYCTRL0_INIT has already done, remove the unnecessary checking of phy_status[1]. Fixes: fde93143469f ("ram: aspeed: Add AST2600 DRAM control support") Review-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-11-23Merge tag 'u-boot-amlogic-20221122' of ↵Tom Rini1-0/+70
https://source.denx.de/u-boot/custodians/u-boot-amlogic - Implement setbrg op to meson serial device - Re-add the old PHY reset binding for nanopi-k2
2022-11-22sandbox: check lseek return value in handle_ufi_commandHeinrich Schuchardt1-3/+7
Invoking lseek() may result in an error. Handle it. Addresses-Coverity-ID: 376212 ("Error handling issues (CHECKED_RETURN)") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-11-22arm: amlogic: add setbrg op to serial deviceEdoardo Tomelleri1-0/+70
Implement setbrg in amlogic/meson serial device with driver model similar to how the meson_uart.c driver does it in Linux. Also configure (probe) the serial device with the new reg5 register. Signed-off-by: Edoardo Tomelleri <e.tomell@gmail.com> Link: https://lore.kernel.org/r/20220918161701.572814-1-e.tomell@gmail.com Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-11-22Merge tag 'xilinx-for-v2023.01-rc3' of ↵Tom Rini10-32/+109
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.01-rc3 microblaze: - Enable 32 bit addressing mode for SPIs zynq: - Minor DT fixes (PL clock enabling) zynqmp: - Disable watchdog by default - Remove unused xlnx,eeprom chosen support - Add missing symlink for vck190 SC revB - Use mdio bus with ethernet-phy-id description versal: - Add mini qspi/ospi configuration versal-net: - Add soc driver - Fix Kconfig entry for SOC - Fix loading address location for MINI configuration - Disable LMB for mini configuration net: - Fix ethernet-phy-id usage in the code pinctrl: - Revert high impedance/output enable support timer: - Fix timer relocation for Microblaze - Fix timer wrap in 32bit Xilinx timer driver
2022-11-22spi: cadence-qspi: Fix compilation error in mini u-boot flash resetAshok Reddy Soma1-2/+2
When cadence_qspi_versal_flash_reset() function is called in mini u-boot where there is no firmware support, it is missing defines for macro's BOOT_MODE_POR_0 & BOOT_MODE_POR_1. Remove them and replace with already define macro's which have same values as these. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20221116141155.14788-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-11-22qspi: versal-net: Add condition for tapdelay registerAshok Reddy Soma1-1/+2
Add CONFIG_ARCH_VERSAL_NET to select tapdelay register for versal-net. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/2500dd688214e2ec2d54ed3fabbfee0b1ca861a6.1668613229.git.michal.simek@amd.com
2022-11-22soc: xilinx: versal-net: Add soc_xilinx_versal_net driverMichal Simek3-0/+87
Add soc_xilinx_versal_net driver to identify the family & revision of versal-net SoC. Add Kconfig option CONFIG_SOC_XILINX_VERSAL_NET to enable/disable this driver. To enable this driver by default, add this config to xilinx_versal_net_virt_defconfig file. This driver will be probed using platdata U_BOOT_DEVICE structure which is specified in mach-versal-net/cpu.c. Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/613d6bcffd9070f62cf348079ed16c120f8fc56f.1668612993.git.michal.simek@amd.com
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