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2023-04-23Merge tag 'u-boot-rockchip-20230421' of ↵Tom Rini27-227/+2725
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add rk3588 evb support; - Update pinctrl for rk3568 and rk3588; - Update rk3288 dts; - Update mmc support for rk3568 and rk3588; - Add rng support for rk3588; - Add DSI support for rk3568; - Some other misc fixes in dts, config, driver;
2023-04-22Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini29-1/+5383
* Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture
2023-04-22Merge https://source.denx.de/u-boot/custodians/u-boot-watchdogTom Rini5-0/+414
- watchdog: arm_smc_wdt: add watchdog support (Lionel) - watchdog: ftwdt010: return a previously deleted driver now ported to DM (Sergei) - watchdog: Add a watchdog driver for Raspberry Pi boards (Etienne)
2023-04-22Merge tag 'u-boot-stm32-20230419' of ↵Tom Rini4-29/+22
https://source.denx.de/u-boot/custodians/u-boot-stm configs: _ Add usb_pgood_delay for ST boards _ increase malloc size for pre-reloc for stm32mp15 _ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15 dts: _ Add QSPI support on STM32MP13x SoC family _ Add FMC support on STM32MP13x SoC family drivers/machine: _ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() _ spi: stm32_qspi: Remove useless struct stm32_qspi_flash _ rawnand: stm32_fmc2: remove unsupported EDO mode _ stm32mp: fix various array bounds checks
2023-04-22mtd: rawnand: nand_base: Handle algorithm selectionLinus Walleij1-4/+25
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the D-Link DIR-885L and DIR-890L routers, we need to explicitly select the ECC like this in the device tree: nand-ecc-algo = "bch"; nand-ecc-strength = <1>; nand-ecc-step-size = <512>; This is handled by the Linux kernel but U-Boot core does not respect this. Fix it up by parsing the algorithm and preserve the behaviour using this property to select software BCH as far as possible. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm] Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-22Revert "mtd: rawnand: nand_base: Handle algorithm selection"Dario Binacchi1-9/+3
It will be replaced by a more recent version which contains fixes for tests run by Tom Rini. This reverts commit ff33d3c87c2a1ab576607c2f67a9cb7690a4e7ca. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-21mmc: rockchip_sdhci: Limit number of blocks read in a single commandJonas Karlman1-0/+8
Using DMA to load TF-A into SRAM fails when booting from eMMC on RK3588. ## Checking hash(es) for Image atf-3 ... sha256 error! Bad hash value for 'hash' hash node in 'atf-3' image node spl_load_simple_fit: can't load image loadables index 2 (ret = -1) mmc_load_image_raw_sector: mmc block read error Fix this by using PIO mode in SPL and limit the number of blocks used in a single read command to avoid triggering Data End Bit Error interrupt. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: sdhci: Allow disabling of SDMA in SPLPeter Geis2-4/+12
Rockchip emmc devices have a similar issue to Rockchip dwmmc devices, where performing DMA to SRAM later causes issues with suspend/resume. Allow us to toggle SDMA in SPL for sdhci similar to ADMA support, so we can ensure DMA is not used when loading the SRAM code. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> [jonas@kwiboo.se: add Kconfig default value and fix ADMA typo] Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21clk: rockchip: rk3588: Add limited TMCLK_EMMC clock supportJonas Karlman1-0/+2
The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Add support for RK3588Jonas Karlman1-4/+53
Add support for RK3588 to the rockchip sdhci driver. Use driver data to handle differences between RK3568 and RK3588: - Set "Receive original clock source is auto gating" for RK3588. - Set "Receive clock source is no-inverted" only on RK3568 and "Transmit clock source is invertion of original clock input" for RK3588. - Use different txclk_tapnum for HS400 modes on RK3588. - Configure the CMDOUT reg for HS400 modes for RK3588. This is based on the mainline linux and vendor kernel driver and have successfully been tested with rock5b-rk3588_defconfig and CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_SPEED_MODE_SET=y using the following command to switch mode and then read 512 MiB of data from eMMC into memory, => mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000 for each of the modes below. 0 = MMC legacy 1 = MMC High Speed (26MHz) 3 = MMC High Speed (52MHz) 4 = MMC DDR52 (52MHz) 10 = HS200 (200MHz) 11 = HS400 (200MHz) 12 = HS400ES (200MHz) Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Fix HS400 and HS400ES mode on RK3568Jonas Karlman1-3/+3
Adjust tap number for transmit clock, tap number and delay number for strobe input to fix HS400 modes on RK3568. New values have been picked from vendor kernel and u-boot and have successfully been tested with rock-3a-rk3568_defconfig and CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_SPEED_MODE_SET=y using the following command to switch mode and then read 512 MiB of data from eMMC into memory, => mmc dev 0 0 <mode> && mmc info && mmc read 10000000 2000 10000 for each of the modes below. 0 = MMC legacy 1 = MMC High Speed (26MHz) 3 = MMC High Speed (52MHz) 4 = MMC DDR52 (52MHz) 10 = HS200 (200MHz) 11 = HS400 (200MHz) 12 = HS400ES (200MHz) Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Rearrange and simplify used regs and flagsJonas Karlman1-27/+13
This rearrange and remove duplicate defines to make the code cleaner. There is no need to read vendor area1 and use an offset each time, it is easier and clearer to just use the reg offset defined in TRM, same as the other vendor regs. This also removes use of the misspelled const for the RK3588 CMDOUT reg, it will be re-added when support for RK3588 is introduced. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Remove empty get_phy and set_enhanced_strobe opsJonas Karlman1-13/+1
Remove empty implementations of get_phy and set_enhanced_strobe ops. Change driver set_enhanced_strobe to return 0 in order to allow missing implementation of the ops. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Update speed mode controls in set_ios_postJonas Karlman1-26/+42
Refactor set_ios_post ops to correctly set UHS Speed Select field values according to TRM. Also set or unset Enhanced Strobe Enable bit and eMMC Card present bit in set_ios_post, the Enhanced Strobe Enable bit was never unset after switching to HS400ES mode. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Refactor execute tuning error handlingJonas Karlman1-24/+11
Check return value from mmc_send_cmd and clear HOST_CONTROL2 when there is an error. Also skip enable of interrupt signaling and remove a delay, a delay is already happening in sdhci_send_command. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Use set_clock and config_dll sdhci_opsJonas Karlman1-13/+15
Change to configure clock and DLL in set_clock and config_dll ops instead of in the set_ios_post ops. With this change the output clock is turned off while configuring DLL parameters, according to the design recommendations. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Add set_clock and config_dll sdhci_opsJonas Karlman1-2/+27
Add support for the set_clock and config_dll sdhci_ops. Use of these ops will allow configuration of DLL while the output clock is disabled. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Remove unneeded emmc_phy_initJonas Karlman1-26/+0
Remove the unneeded emmc_phy_init now that the no-inverter flag is handled correctly after commit 2321a991bbb5 ("rockchip: sdhci: rk3568: bypass DLL when clk <= 52 MHz"). Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: rockchip_sdhci: Fix use of device private dataJonas Karlman1-7/+9
The device private data is misused in rockchip_sdhci_of_to_plat and rockchip_sdhci_execute_tuning. In these functions dev_get_priv is assigned to struct sdhci_host: struct sdhci_host *host = dev_get_priv(dev); Instead, the sdhci host should refer to host in struct rockchip_sdhc: struct rockchip_sdhc *priv = dev_get_priv(dev); struct sdhci_host *host = &priv->host; Because host is the first member in struct rockchip_sdhc this is not a real problem, lets fix it anyway and also use priv name consistently. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: sdhci: Set UHS Mode Select field for UHS SDR25 modeJonas Karlman1-0/+4
Set correct UHS Mode Select field value for UHS SDR25 (50MHz) mode. Fixes: d1c0a2200afb ("mmc: sdhci: Add support for HOST_CONTROL2 and setting UHS timings") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21mmc: sdhci: Fix HISPD bit handling for MMC HS 52MHz modeJonas Karlman1-0/+1
Set High Speed Enable bit for MMC High Speed (52MHz) mode. Fixes: f12341a95295 ("mmc: sdhci: Fix HISPD bit handling") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rng: add trngv1 for rk3588Chris Morgan2-11/+114
This adds support for the TRNG found in the RK3588 SoC to the rockchip_rng driver so that it can be used for things such as seeding randomness to Linux. Changes in V3: - Moved notes from commit to cover letter. - Added Reviewed-By tag. Changes in V2: - Modified Kconfig to note that the Rockchip RNG driver supports all versions of the hardware (v1, v2, and the trng in the rk3588). Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock supportJonas Karlman1-0/+2
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock in assigned-clocks, add dummy support to set parent of this clock to the rk3568 cru driver. Fixes probe of pmic driver and missing regulators on affected boards, rk3568-evb and rk3568-rock-3a. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21pinctrl: rockchip: Fix IO mux selection on RK3568Jonas Karlman1-28/+38
IO mux selection is not working correctly for all pins. Sync mux route data from linux to add any missing and update wrong trigger pins to fix this. Also apply the pull-up fix needed for GPIO0 D3-D6. Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21rockchip: rk3588: Add support for sdmmc clocks in SPLJonas Karlman1-0/+125
Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: scmi: Add Kconfig option for SPLJonas Karlman3-2/+10
Building U-Boot SPL with CLK_SCMI and SCMI_FIRMWARE Kconfig options enabled and SPL_FIRMWARE disabled result in the following error. drivers/clk/clk_scmi.o: in function `scmi_clk_gate': drivers/clk/clk_scmi.c:84: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:88: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_get_rate': drivers/clk/clk_scmi.c:113: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:117: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_set_rate': drivers/clk/clk_scmi.c:139: undefined reference to `devm_scmi_process_msg' drivers/clk/clk_scmi.c:143: undefined reference to `scmi_to_linux_errno' drivers/clk/clk_scmi.o: in function `scmi_clk_probe': drivers/clk/clk_scmi.c:157: undefined reference to `devm_scmi_of_get_channel' make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make: *** [Makefile:2043: spl/u-boot-spl] Error 2 Add Kconfig option so that CLK_SCMI can be disabled in SPL to fix this. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: otp: fix misc_read() return valuesJohn Keeping1-4/+8
The documentation for misc_read() says: Return: number of bytes read if OK (may be 0 if EOF), -ve on error The Rockchip efuse driver implements this so it should return the number of bytes read rather than zero on success. Fix this so that the driver follows the usual contract for read operations. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: efuse: fix misc_read() return valuesJohn Keeping1-4/+8
The documentation for misc_read() says: Return: number of bytes read if OK (may be 0 if EOF), -ve on error The Rockchip efuse driver implements this so it should return the number of bytes read rather than zero on success. Fix this so that the driver follows the usual contract for read operations. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: video: Add support for RK3568 DSI HostChris Morgan4-0/+916
Add support for DSI Host controller on Rockchip RK3568. This driver is heavily based on the Rockchip dw_mipi_dsi_rockchip.c driver in Linux and the stm32_dsi.c driver in U-Boot. It should be easy to add support for other SoCs as the only missing component from the mainline driver is setting the VOP big or VOP little (which the rk3568 does not have). Driver was tested for use in sending commands to a DSI panel in order to obtain the panel ID. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21drivers: phy: add Innosilicon DSI-DPHY driverChris Morgan3-0/+689
Add support for the Innosilicon DSI-DPHY driver for Rockchip SOCs. The driver was ported from Linux and tested on a Rockchip RK3566 based device to query the panel ID via a DSI command. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21ram: rk3399: add missing high row detectionJonathan Liu1-0/+2
For 2 GB LPDDR4 single-rank RAM with 16 rows, the Rockchip ddr init bin prints: "Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB" U-Boot TPL prints: "BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB" Add missing high row detection so that U-Boot TPL prints Row=16, same as the Rockchip ddr init bin: "BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB" Signed-off-by: Jonathan Liu <net147@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21gpio: rockchip: Add support for RK3568 and RK3588 banksJonas Karlman1-36/+76
The GPIO V2 controller on RK3568 and RK3588 works very similar to prior generation, main difference is the use of a write mask in the upper 16 bits and register address offset have changed. GPIO_VER_ID is a new register at 0x0078 that is used to determine when the driver should use new or old register offsets and values. Earlier generation return 0x0 from this offset. Refactor code and add support for the GPIO V2 controller used in RK3568 and RK3588. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: gpio: rk_gpio: use ROCKCHIP_GPIOS_PER_BANK as dividerJohan Jonker1-1/+1
The current divider to calculate the bank ID can change. Given the Rockchip TRM not all gpio-banks have 32 pins per bank. The "gpio-ranges" syntax allows multiple items with variable number of pins. Use a constant ROCKCHIP_GPIOS_PER_BANK as fixed divider. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: rockchip: clk_rk3288: add PCLK_RKPWMJohan Jonker1-0/+1
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM instead of PCLK_PWM. They have the same pclk_cpu parent, so add PCLK_RKPWM to rk3288_clk_get_rate(). Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21video: rockchip: rk_vop: add rk3288-dp compare stringJohan Jonker1-1/+2
In the current rk3288.dtsi file the compatible string for the DisplayPort(DP) node ends with "edp". The string in the binding ends with "dp" which conflicts with "cdn-dp" as a search term. Add "rk3288-dp" as compare string to select vop_id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21pinctrl: rockchip: support rk3588 pinctrlJianqun Xu3-0/+541
Add support for Rockchip rk3588 variant of pinctrl. The driver is adapted from the Linux driver. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> [eugen.hristev@collabora.com: port to latest U-boot, bring more changes from Linux use translated pull values table] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
2023-04-21rockchip: sdhci: rk3568: fix clock setting logicVasily Khoruzhick1-3/+3
mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post uses it if its != 0, regardless of mmc->clock value, and it breaks eMMC controller. Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for breaking eMMC, since first initialization sets mmc->mmc_tran speed to non-zero value (26MHz in my case), and on subsequent re-init when mmc layer asks for 400KHz it sets 26MHz instead. Fix it by using MAX(mmc->tran_speed, mmc->clock) Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-20ram: starfive: add ddr driverYanhong Wang10-1/+3202
Add driver for StarFive JH7110 to support ddr initialization in SPL. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20pinctrl: starfive: Add StarFive JH7110 driverKuan Lim Lee8-0/+1001
Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20clk: starfive: Add StarFive JH7110 clock driverYanhong Wang7-0/+1004
Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoCYanhong Wang3-0/+175
Add a DM reset driver for StarFive JH7110 SoC. Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20cache: starfive: Add StarFive JH7110 supportYanhong Wang1-0/+1
This adds support for the StarFive JH7110 SoC which also feature this SiFive cache controller. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-19stm32mp: fix various array bounds checksRasmus Villemoes1-1/+1
In all these cases, the index on the LHS is immediately afterwards used to access the array appearing in the ARRAY_SIZE() on the RHS - so if that index is equal to the array size, we'll access one-past-the-end of the array. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19mtd: rawnand: stm32_fmc2: remove unsupported EDO modeChristophe Kerello1-0/+3
Remove the EDO mode support from as the FMC2 controller does not support the feature. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-19spi: stm32_qspi: Remove useless struct stm32_qspi_flashPatrice Chotard1-24/+3
Currently, in stm32_qspi_claim_bus(), QSPI_CR and QSPI_DCR registers are saved in stm32_ospi_flash struct on first flash memory initialization and restored on each flash accesses. As the logic of spi-uclass.c changed since 'commit 741280e9accd ("spi: spi-uclass: Fix spi_claim_bus() speed/mode setup logic")' set_speed() and set_mode() callbacks are called systematically when bus speed or bus mode need to be updated, QSPI_CR and QSPI_DCR registers are set accordingly. So stm32_qspi_claim_bus() can be updated by removing QSPI_CR and QSPI_DCR save/restore code and struct stm32_ospi_flash can be removed as well. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()Patrice Chotard1-4/+15
For debug purpose, it should be useful to indicate the slew rate for each pins. Add ospeed register information for pins which are configured in either alternate function or gpio output. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-18watchdog: arm_smc_wdt: add watchdog supportLionel Debieve3-0/+132
Implement a ARM SMCCC based driver that allow to use a secure watchdog on the platform. Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-18watchdog: ftwdt010: return a previously deleted driver now ported to DMSergei Antonov3-0/+140
The ftwdt010 watchdog driver was deleted by commit 11232139e399 ("nds32: Remove the architecture") Return it to the codebase in a DM compatible form. Enable it in sandbox_defconfig to test compilability. Another platform using ftwdt010 will be submitted later. Signed-off-by: Sergei Antonov <saproj@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-04-18watchdog: Add a watchdog driver for Raspberry Pi boardsETIENNE DUBLE3-0/+142
This driver supports the bcm2835 watchdog found on Raspberry Pi boards. It is derived from the Linux driver and was tested on two Raspberry Pi board versions (B+ and 3B+). Signed-off-by: Etienne Dublé <etienne.duble@imag.fr> Reviewed-by: Stefan Roese <sr@denx.de>
2023-04-17Merge tag 'u-boot-nand-20230417' of ↵Tom Rini6-5/+167
https://source.denx.de/u-boot/custodians/u-boot-nand-flash Pull request for u-boot-nand-20230417 The first two patches are by Frieder Schrempf who joins as a reviewer for the SPI NAND framework and drivers. The following 2 patches are by Linus Walleij and are taken by the series "Add Broadcom Northstar basic support". Bin Meng makes static a list for octeontx. Francesco Dolcini specifies MTD partitions on command line for colibri-{imx6ull,imx7}.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 09:21:56 +0000