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path: root/drivers/spi
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2018-04-27Convert CONFIG_SPI to KconfigAdam Ford3-20/+5
This converts the following to Kconfig: CONFIG_SPI This partly involves updating code that assumes that CONFIG_SPI implies things that are specific to the MPC8xx SPI driver. For now, just update the CONFIG tests. This also involves reworking the default for CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a reasonable default, as it does not cause any compile failures. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-23spi: dw: invert wait condition in dw_spi_xferEugeniy Paltsev1-1/+1
While switching to readl_poll_timeout macros from custom code the waiting condition was accidently inverted, so it was pure luck that this code works at least in some conditions. Fix that by inverting exit condition for readl_poll_timeout. Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush") Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-04-11spi: sh_qspi: Make use of the 32byte FIFOMarek Vasut1-10/+24
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing the SPI transmission 1 byte at time, if there is a 32byte chunk of data to be transferred, fill the FIFO completely and then transfer the data to/from the FIFO. This increases the SPI NOR access speed significantly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11spi: sh_qspi: Replace ad hoc waiting with wait_for_bitMarek Vasut1-14/+9
Replace the ad-hoc endless loops with wait_for_bit() with reasonable timeout. Note that the loops had internal 10uS delays, although there is no reason for those on this HW, so they are dropped. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11spi: sh_qspi: Drop SPBDCR waitMarek Vasut1-8/+0
Waiting for SPBDCR == 1 is not required and is covered by the subsequent wait for SPSR_SPRFF, so drop this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11spi: sh_qspi: Replace data types with short onesMarek Vasut1-31/+31
Just replace unsigned {char,short,long} with u{8,16,32}, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11mtd: spi: Add Renesas RPC SPI-flash driverMarek Vasut3-0/+474
Add driver for the RPC block in SPI-flash mode. This driver allows access to a SPI NOR flash attached to the RPC block and does not support RPC in Hyperflash mode. Note that this block is extremely selective when communicating with the SPI NOR. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-07Revert "spi: atmel: Drop non-dm code"Tom Rini2-0/+217
As we aren't quite able to convert some platforms with a very small size limit in SPL yet, we need to revert this for now. This reverts commit 7b0947787358c6b277431d6b76ce043d8bec641d. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-07Revert "spi: atmel: Drop atmel_spi.h"Tom Rini2-88/+93
As we aren't quite able to convert some platforms with a very small size limit in SPL yet, we need to revert this for now. This reverts commit 37434db29be495ef41f204a97b8bf13b1418f97d. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-06powercp: mpc8xx: move commproc.hChristophe Leroy1-1/+1
include/commproc.h is dedicated to the 8xx, rename it cpm_8xx.h and move it into arch/powerpc/include/asm Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06powerpc: mpc8xx: Change CONFIG_8xx to CONFIG_MPC8xxChristophe Leroy1-1/+1
CONFIG_8xx doesn't mean much outside of arch/powerpc/ This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ... It also renames 8xx_immap.h to immap_8xx.h to be consistent with other file names. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06spi: atmel: default y if DM_SPI && ARCH_AT91Jagan Teki1-1/+1
ATMEL_SPI is now fully converted to driver-model and respective boards switch to DM_SPI as well, so make default y for ARCH_AT91 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06spi: atmel: Drop atmel_spi.hJagan Teki2-93/+88
atmel_spi.h has register offsets, and atmel_spi_slave structure, move it into .c file for better readability and drop atmel_spi.h Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06spi: atmel: Drop non-dm codeJagan Teki2-217/+0
All board configs are now enabled DM_SPI for SPL and U-Boot proper, so now its time to drop non-dm code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06spi: atmel: Add ifdef for DM_GPIO codeJagan Teki1-2/+12
Few boards are configuring gpio directly from board instead using drivers/gpio so add ifdef for DM_GPIO to compatible for both the cases. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-03-23omap3: spi: Correct ti, pindir-d0-out-d1-in parsingSjoerd Simons1-2/+4
The ti,pindir-d0-out-d1-in property is not expected to have a value according to the device-tree binding, so treat it as a boolean not a uint property. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22DW SPI: use 32 bit access instead of 16 and 32 bit mixEugeniy Paltsev1-25/+15
Current DW SPI driver uses 32 bit access for some registers and 16 bit access for others. So if DW SPI IP is connected via bus which doesn't support 16 bit access we will get bus error. Fix that by switching to 32 bit access only instead of 16 and 32 bit mix Additional Documentation to Support this Change: The DW_apb_ssi databook states: "All registers in the DW_apb_ssi are addressed at 32-bit boundaries to remain consistent with the AHB bus. Where the physical size of any register is less than 32-bits wide, the upper unused bits of the 32-bit boundary are reserved. Writing to these bits has no effect; reading from these bits returns 0." [1] [1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22DW SPI: add option to use external gpio for chip selectEugeniy Paltsev1-1/+50
DW SPI internal chip select management has limitation: it hold CS line in active state only when the FIFO is not empty. If the FIFO freed before we add new data the SPI transaction will be broken. So add option to use external gpio for chip select. Gpio can be added via device tree using standard gpio bindings. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22DW SPI: refactor poll_transfer functionsEugeniy Paltsev1-22/+4
There is no sense in waiting for RX data in dw_reader function: there is no chance that RX data will appear in RX FIFO if RX FIFO is empty after previous TX write in dw_writer function. So get rid of this waiting. After that we can get rid of dw_reader return value and make it returning void. After that we can get rid of dw_reader return value check in poll_transfer function. With these changes we're getting closer to Linux DW SPI driver. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22DW SPI: fix transmit only modeEugeniy Paltsev1-1/+5
In current implementation we get -ETIMEDOUT error when we try to use transmit only mode (SPI_TMOD_TO) This happens because in transmit only mode input FIFO never gets any data which breaks our logic in dw_reader(): we are waiting until RX data will be ready in dw_reader, but this newer happens, so we return with error. Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use RX FIFO. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22DW SPI: fix tx data loss on FIFO flushEugeniy Paltsev1-0/+15
In current implementation if some data still exists in Tx FIFO it can be silently flushed, i.e. dropped on disabling of the controller, which happens when writing 0 to DW_SPI_SSIENR (it happens in the beginning of new transfer) So add wait for current transmit operation to complete to be sure that current transmit operation is finished before new one. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-15Merge git://git.denx.de/u-boot-spiTom Rini3-101/+25
2018-03-14spi: omap3: Fix redeclared errorJagan Teki1-2/+2
omap3_spi_set_speed|mode redeclared bus symbol, fix the same. error: drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’: drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol struct udevice *bus = dev->parent; Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13board: stm32: switch to DM STM32 timerPatrice Chotard1-1/+0
Use available DM stm32_timer driver instead of dedicated mach-stm32/stm32fx/timer.c. Remove all defines or files previously used for timer usage in arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx Enable DM STM32_TIMER for STM32F4/F7 and H7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13spi: omap3: Skip set_mode, set_speed from claimJagan Teki1-5/+16
set_mode, set_seed functions has separate function pointers in dm_spi_ops, so use them in relevent one instead of calling from claim_bus. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13spi: atcspi200: Drop non-dm codeJagan Teki2-94/+7
Boards adp-ae3xx_defconfig, nx25-ae250_defconfig already enabled DM_SPI, so non-dm code make no use of it hence droped. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-02-13spi: Migrate CONFIG_CF_SPI to KconfigTuomas Tynkkynen1-0/+6
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_KIRKWOOD_SPI to KconfigTuomas Tynkkynen1-0/+6
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_LPC32XX_SSP to KconfigTuomas Tynkkynen1-0/+5
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MPC8XXX_SPI to KconfigTuomas Tynkkynen1-0/+5
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MXC_SPI to KconfigTuomas Tynkkynen1-0/+6
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_MXS_SPI to KconfigTuomas Tynkkynen1-0/+6
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_SH_QSPI to KconfigTuomas Tynkkynen1-0/+6
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13spi: Migrate CONFIG_SH_SPI to KconfigTuomas Tynkkynen1-0/+6
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-07atcspi200: avoid possible NULL dereferenceHeinrich Schuchardt1-2/+2
Check if ns before and not after dereferencing it. Indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-01-26Merge git://git.denx.de/u-boot-spiTom Rini14-122/+1057
2018-01-26DW SPI: Get clock value from Device TreeEugeniy Paltsev1-2/+43
Add option to set spi controller clock frequency via device tree using standard clock bindings. Define dw_spi_get_clk function as 'weak' as some targets (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API and implement dw_spi_get_clk their own way in their clock manager. Get rid of clock_manager.h include as we don't use cm_get_spi_controller_clk_hz function anymore. (we use redefined dw_spi_get_clk in SOCFPGA clock managers instead) Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: cadence_qspi_apb: Make flash writes 32 bit alignedVignesh R1-6/+25
Make flash writes 32 bit aligned by using bounce buffers to deal with non 32 bit aligned buffers. This is required because as per TI K2G TRM[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer. Otherwise indirect writes is known to fail sometimes. [1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when ↵Vignesh R1-20/+6
possible" This reverts commit 57897c13de03ac0136d64641a3eab526c6810387. Using bounce_buf.c to handle non-DMA alignment problems is bad as bounce_buf.c does cache manipulations which is not required. Therefore revert this patch in favour of local bounce buffer solution in the next patch. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when ↵Goldschmidt Simon1-16/+10
possible" This reverts commit b63b46313ed29e9b0c36b3d6b9407f6eade40c8f. This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates the data cache after reading. This is meant for dma transfers only and breaks the cadence_qspi driver which copies via cpu only: data that is copied by the cpu is in cache only and the cache invalidation at the end throws away this data. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jason Rush <jarush@gmail.com> Acked-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: cadence_spi: Sync DT bindings with LinuxJason Rush3-20/+21
Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R <vigneshr@ti.com> Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Signed-off-by: Jason Rush <jarush@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Acked-by: Marek Vasut <marex@denx.de>
2018-01-24spi: kirkwood_spi: implement workaround for FE-9144572Chris Packham1-3/+66
Erratum NO. FE-9144572: The device SPI interface supports frequencies of up to 50 MHz. However, due to this erratum, when the device core clock is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and CPOL=CPHA=1 there might occur data corruption on reads from the SPI device. Implement the workaround by setting the TMISO_SAMPLE value to 0x2 in the timing1 register. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24spi: spi-uclass: Fix style violationsMario Six1-3/+2
Remove a superfluous newline, and reduce the scope of a variable. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Remove spi_setup_slave_fdtMario Six1-16/+0
A previous patch removed the spi_flash_probe_fdt function, which contained the last call of the spi_setup_slave_fdt function, which is now equally obsolete. This patch removes the function. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Remove obsolete spi_base_setup_slave_fdtMario Six1-20/+0
0efc024 ("spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT node") added a helper function spi_base_setup_slave_fdt to to set up a SPI slave from a given FDT blob. The only user was the exynos SPI driver. But commit 73186c9 ("dm: exynos: Convert SPI to driver model") removed the use of this function, hence rendering it obsolete. Remove this function, as well as the CONFIG_OF_SPI option, which guarded only this function. Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24spi: Fix style violation and improve codeMario Six1-3/+4
This patch fixes a printf specifier style violation, reduces the scope of a variable, and turns a void pointer that is used with pointer arithmetic into a u8 pointer. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24dm: spi: add BCM63xx HSSPI driverÁlvaro Fernández Rojas3-0/+423
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24dm: spi: add BCM63xx SPI driverÁlvaro Fernández Rojas3-0/+442
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24wait_bit: use wait_for_bit_le32 and remove wait_for_bitÁlvaro Fernández Rojas4-28/+30
wait_for_bit callers use the 32 bit LE version Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-22Convert CONFIG_DAVINCI_SPI to KconfigAdam Ford1-0/+6
This converts the following to Kconfig: CONFIG_DAVINCI_SPI Signed-off-by: Adam Ford <aford173@gmail.com>
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