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2024-07-25Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsungTom Rini3-0/+305
2024-07-24rng: Add Exynos TRNG driverSam Protsenko3-0/+305
Add True Random Number Generator (TRNG) driver for Exynos chips. This implementation is heavily based on Linux kernel's counterpart [1]. It also follows upstream dt-bindings [2]. TRNG block is usually a part of SSS (Security Sub System) IP-core on Exynos chips. Because SSS access on Exynos850 is protected by TZPC (TrustZone Protection Control), it's not possible to read/write TRNG registers from U-Boot, as it's running in EL1 mode. Instead, the corresponding SMC calls should be used to make the secure software running in EL3 mode access it for us. Those SMC calls are handled by LDFW (Loadable Firmware), which has to be loaded first. For example, for E850-96 board it's done in its board_init(), so by the time RNG capabilities are needed the LDFW should be already loaded and TRNG should be functional. [1] drivers/char/hw_random/exynos-trng.c [2] dts/upstream/Bindings/rng/samsung,exynos5250-trng.yaml Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-07-18driver: rng: Do not check ARM_SMCCC_TRNG_VERSIONLeo Yan1-4/+0
As described in the document SMC Calling Convention (ARM DEN 0028 1.5 F), section 7 "Arm Architecture Calls", the SMC call SMCCC_ARCH_FEATURES is not expected to support the function ID ARM_SMCCC_TRNG_VERSION. Trusted Firmware-A follows up the specification in its implementation. This commit removes the invocation to avoid the failure - which is a wrong calling in U-boot. The later code invokes ARM_SMCCC_TRNG_VERSION for retrieving the TRNG version, except it can read back the version number, it also can be used to detect whether the TRNG is supported or not. Signed-off-by: Leo Yan <leo.yan@arm.com> Reviewed-by: Weizhao Ouyang <o451686892@gmail.com>
2024-05-05rng: Introduce SPL_DM_RNGMarek Vasut2-1/+8
Add SPL variant of DM_RNG so that the DM_RNG can be disabled in SPL if necessary. This may be necessary due to e.g. size constraints of the SPL. Signed-off-by: Marek Vasut <marex@denx.de>
2024-04-22common: Convert *.c/h from UTF-8 to ASCII enconfingMichal Simek1-3/+3
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
2024-03-15Merge tag 'u-boot-rockchip-20240315' of ↵Tom Rini1-2/+9
https://source.denx.de/u-boot/custodians/u-boot-rockchip into next Please pull the updates for rockchip platform: - Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC, Toybrick TB-RK3588X; rk3588s Cool Pi 4B; rk3566 Pine64 PineTab2; - Add saradc v2 support; - Add PMIC RK806 support; - rk3588 disable force_jtag by default; - Migrate to use IO-domain driver for all boards; - Use common bss and stack addresses for rk33xx and rk35xx boards; - Other updates for driver, config and dts;
2024-03-14rng: rockchip: Use same compatible as linuxJonas Karlman1-1/+9
Replace the rockchip,cryptov1-rng compatible with compatibles used in the linux device tree for RK3288, RK3328 and RK3399 to ease sync of SoC device tree from linux. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2024-03-13driver: rng: Fix SMCCC TRNG crashWeizhao Ouyang1-1/+1
Fix a SMCCC TRNG null pointer crash due to a failed smccc feature binding. Fixes: 53355bb86c25 ("drivers: rng: add smccc trng driver") Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Weizhao Ouyang <o451686892@gmail.com>
2024-03-13rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.hQuentin Schulz1-1/+0
The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-03-11Merge tag 'v2024.04-rc4' into nextTom Rini3-0/+132
Prepare v2024.04-rc4
2024-03-05rng: Add Turris Mox rTWM RNG driverMax Resch3-0/+132
A RNG driver for Armada 3720 boards running the Turris Mox rWTM firmware from CZ.NIC in the secure processor. Signed-off-by: Max Resch <resch.max@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2024-03-02rng: eliminate common.h include from RNG driversHeinrich Schuchardt11-21/+9
Usage of common.h is deprecated. * Remove common.h from RNG drivers. * Sort includes. * Add time.h to sandbox driver. * Add linux/types.h to rng.h to provide size_t. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-09rng: detect RISC-V Zkr RNG device in bind methodHeinrich Schuchardt1-8/+26
The existence of devices should be checked in the bind method and not in the probe method. Adjust the RISC-V Zkr RNG driver accordingly. Use ENOENT (and not ENODEV) to signal that the device is not available. Fixes: ceec977ba1a9 ("rng: Provide a RNG based on the RISC-V Zkr ISA extension") Reported-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-01-09rng: fix ARMv8.5 RNDR driverHeinrich Schuchardt1-3/+3
In different parts of our code we assume that the first RNG device is the one to be used. Therefore it is preferable to detect the availability of the RNDR register already in the bind method. For signaling the non-existence of a device the driver model requires using ENOENT (and not ENODEV). Fixes: 31565bb0aa2d ("driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registers") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Andre Przywara <andre.przywara@arm.com>
2023-11-02rng: Add StarFive JH7110 RNG driverChanho Park3-0/+281
Adds to support JH7110 TRNG driver which is based on linux kernel's jh7110-trng.c. This can support to generate 256-bit random numbers and 128-bit but this makes 256-bit default for convenience. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02rng: Provide a RNG based on the RISC-V Zkr ISA extensionHeinrich Schuchardt3-0/+125
The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It provides an interface to a physical entropy source. A RNG driver based on the seed CSR is provided. It depends on mseccfg.sseed being set in the SBI firmware. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-13drivers: rng: add support for Meson S4Alexey Romanov1-1/+71
For some Amlogic SOC's, mechanism to obtain random number has been changed. For example, S4 now uses status bit waiting algo. Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231012075828.22685-2-avromanov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-10-11driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registersAndre Przywara3-0/+89
The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS system registers, that provide 64 bits worth of randomness on every read. Since it's an extension, and implementing it is optional, there is a field in the ID_AA64ISAR0_EL1 ID register to query the availability of those registers. Add a UCLASS_RNG driver that returns entropy via repeated reads from those system registers, if the extension is implemented. The driver always binds, but checks the availability in the probe() routine. This helps systems which suffer from low boot entropy, since U-Boot can provide entropy via the generic UEFI entropy gathering protocol to the OS, at an early stage. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-04rng: stm32: Implement custom RNG configuration supportGatien Chevallier1-3/+51
STM32 RNG configuration should best fit the requirements of the platform. Therefore, put a platform-specific RNG configuration field in the platform data. Default RNG configuration for STM32MP13 is the NIST certified configuration [1]. While there, fix and the RNG init sequence to support all RNG versions. [1] https://csrc.nist.gov/projects/cryptographic-module-validation-program/entropy-validations/certificate/53 Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: add error concealment sequenceGatien Chevallier1-23/+140
Seed errors can occur when using the hardware RNG. Implement the sequences to handle them. This avoids irrecoverable RNG state. Try to conceal seed errors when possible. If, despite the error concealing tries, a seed error is still present, then return an error. A clock error does not compromise the hardware block and data can still be read from RNG_DR. Just warn that the RNG clock is too slow and clear RNG_SR. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: add RNG clock frequency restraintGatien Chevallier1-5/+38
In order to ensure a good RNG quality and compatibility with certified RNG configuration, add RNG clock frequency restraint. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: Implement configurable RNG clock error detectionGatien Chevallier1-5/+17
RNG clock error detection is now enabled if the "clock-error-detect" property is set in the device tree. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-10-04rng: stm32: rename STM32 RNG driverGatien Chevallier3-5/+5
Rename the RNG driver as it is usable by other STM32 platforms than the STM32MP1x ones. Rename CONFIG_RNG_STM32MP1 to CONFIG_RNG_STM32 Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Grzegorz Szymaszek <gszymaszek@short.pl> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-21rockchip: rng: add trngv1 for rk3588Chris Morgan2-11/+114
This adds support for the TRNG found in the RK3588 SoC to the rockchip_rng driver so that it can be used for things such as seeding randomness to Linux. Changes in V3: - Moved notes from commit to cover letter. - Added Reviewed-By tag. Changes in V2: - Modified Kconfig to note that the Rockchip RNG driver supports all versions of the hardware (v1, v2, and the trng in the rk3588). Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com> Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-14drivers: rng: optee_rng: register to CONFIG_OPTEE_SERVICE_DISCOVERYEtienne Carriere2-1/+7
Changes optee_rng driver to register itself has a OP-TEE service so that a device is bound for the driver when OP-TEE enumerates the PTA RNG service. Cc: Sughosh Ganu <sughosh.ganu@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-08-02tpm: rng: Add driver model interface for TPM RNG deviceSughosh Ganu3-0/+33
The TPM device has a builtin random number generator(RNG) functionality. Expose the RNG functions of the TPM device to the driver model so that they can be used by the EFI_RNG_PROTOCOL if the protocol is installed. Also change the function arguments and return type of the random number functions to comply with the driver model api. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2022-07-12rng: stm32mp1_rng: add conditional reset feature for STM32MP13xLionel Debieve1-14/+47
New IP adds a conditional reset that impact the clock error management. It is now linked to a new compatible. Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-06-23drivers: rng: add smccc trng driverEtienne Carriere3-0/+217
Adds random number generator driver using Arm SMCCC TRNG interface to get entropy bytes from secure monitor. The driver registers as an Arm SMCCC feature driver to allow PSCI driver to bind a device for when secure monitor exposes RNG support from Arm SMCCC TRNG interface. Cc: Sughosh Ganu <sughosh.ganu@linaro.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2022-06-10rng: nuvoton: Add NPCM7xx rng driverJim Liu3-0/+164
Add Nuvoton BMC NPCM750 rng driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-04-11rng: add OP-TEE based Random Number GeneratorPatrick Delaunay3-0/+194
Add driver for OP-TEE based Random Number Generator on ARM SoCs where hardware entropy sources are not accessible to normal world and the RNG service is provided by a HWRNG Trusted Application (TA). This driver is based on the linux driver: char/hw_random/optee-rng.c Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-02-25clk: Add clk_get_by_name_optionalSean Anderson1-2/+2
This adds a helper function for clk_get_by_name in cases where the clock is optional. Hopefully this helps point driver writers in the right direction. Also convert some existing users. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220115205247.566210-2-seanga2@gmail.com
2021-08-31Kconfig: Remove all default n/no optionsMichal Simek1-3/+0
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-06dm: define LOG_CATEGORY for all uclassPatrick Delaunay1-0/+2
Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-02rng: iproc_rng200: Enable support for RPi4 armv7Matthias Brugger1-4/+4
On the RPi4 armv7 build we have the situationt that we use physical addresses of 64 bit, while the virtual addresses are 32 bit. Remap the base address in this scenario via map_physmem(). Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-02-24rng: iProc rng200: Rename ..._platdata variables to just ..._platPeter Robinson1-10/+10
In 8a8d24bd Simon dropped data from all the various _platdata calls but it seems this wasn't caught for the RNG200 driver from when it was posted to merged. This fixes that issue. Fixes: 537f0018 (rng: Add iProc RNG200 driver) Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2021-02-18config: Enable iProc RNG200 driver in RPi4 configsMatthias Brugger1-1/+0
We find the iProc RNG200 in the Raspberry Pi 4. Add it to all it's config so that it can be used. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> [mb: drop rpi_4_32b_defconfig] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-02-16rng: Add iProc RNG200 driverMatthias Brugger3-0/+193
Add support for random number generator RNG200. This is for example found on RPi4. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> [mb: adapt to new struct driver memebers] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-12-13dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass3-21/+21
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass3-7/+7
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2-8/+8
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2-2/+2
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass4-4/+4
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-10-22rng: Add Qualcomm MSM PRNG driverRobert Marko3-0/+151
Add support for the hardware pseudo random number generator found in Qualcomm SoC-s. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-28rng: meson: make core clock optionalNeil Armstrong1-1/+2
This fixes HWRNG support on Amlogic GXL, GXM, G12A, G12B & SM1 based boards dues to the lack of the core clock in the device tree. It was reported breaking EFI boot in the Linux EFI stub, because the EFI_RNG_PROTOCOL didn't check for the RNG device presence before installing itself. The Linux amlogic,meson-rng.yaml doesn't mandate the core clock, this the clock should be ignores if not present. Nevertheless, the clock should be present and this should be fixed on the Linux meson-gxl.dtsi & meson-g12-common.dtsi then synced with U-Boot. The change has been tested on a Khadas VIM3, which uses the common meson-g12-common.dtsi like the Odroid-C4 & Odroid-N2 in Scott's report, along with the RNG cmd. Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Reported-by: Scott K Logan <logans@cottsay.net> Fixes: bc40eb278b ("drivers/rng: add Amlogic hardware RNG driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Scott K Logan <logans@cottsay.net> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-18rng: stm32mp1: use log() instead of printf()Heinrich Schuchardt1-1/+3
The logging system provides flexible filtering and enhanced output. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass2-0/+2
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-29rockchip: rng: Add a driver for random number generator(rng) deviceLin Jinhan3-0/+233
Add a driver for the rng device found on rockchip platforms. Support rng module of crypto v1 and crypto v2. Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 09:24:14 +0000