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2020-07-07ram: stm32mp1: add size and addr parameter to test allPatrick Delaunay1-3/+44
Add size and addr parameter to test "All" to override the default value (4kB and STM32_DDR_BASE) used in tests with these optional parameters: [size] or [addr]. When other optional parameters are present before [addr], they are replaced by default value: - [loop] = "1" - [pattern] = "-" (new: force default pattern) Example to use: DDR>test 0 1 0x20000 DDR>test 0 1 0x1000000 0xD0000000 Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: use the DDR size by default in the test addressBusPatrick Delaunay1-1/+2
The test 4 = "AddressBus [size] [addr]" without parameter detects alias for any address bit only when: - size = real size of DDR - addr = start of DDR = 0xC0000000 These value must be the default value when parameters are absent. This patch sets bufsize to STM32_DDR_SIZE and get_bufsize() selects the correct value for bufsize when this parameter is absent = full size of the DDDR On EV1 board : DDR> test 4 running at 0xC0000000 length 0x40000000 On DK2 board DDR> test 4 running at 0xC0000000 length 0x20000000 Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: add parameter addr in test FrequencySelectivePatternPatrick Delaunay1-6/+7
Add a parameter addr in test FrequencySelectivePattern to select the base address used to execute the tests. Default value (when the parameter is absent) is STM32_DDR_BASE, selected in get_addr() function. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-07ram: stm32mp1: protect minimum value in get_bufsizePatrick Delaunay1-18/+19
Add protection on minimum value for result of get_bufsize and check the alignment of buffer size: only multiple min_size is allowed; only 4 bytes alignment was checked previously (value & 0x3). For example the "Random" test raises an issue when size is not 8 bytes aligned because address for buffer = address + size / 2 is not word aligned. This patch avoid test error for unsupported size value. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-04sifive: fu540: add ddr driverPragnesh Patel5-0/+432
Add driver for fu540 to support ddr initialization in SPL. This driver is based on FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass8-0/+8
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass14-0/+14
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass17-0/+17
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18command: Remove the cmd_tbl_t typedefSimon Glass1-5/+6
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass8-0/+8
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass2-0/+2
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-14ram: stm32mp1: Add support for multiple configsMarek Vasut1-5/+28
Add support for multiple DRAM configuration subnodes, while retaining the support for a single flat DRAM configuration node. This is useful on systems which can be manufactured in multiple configurations and where the DRAM configuration can be determined at runtime. The code is augmented by a function which can be overridden on board level, allowing a match on the configuration node name, very much like the fitImage configuration node name matching works. The default match is on the single top-level DRAM configuration, if matching on subnodes is required, then this board_stm32mp1_ddr_config_name_match() must be overridden. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-15configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOTPatrick Delaunay1-1/+1
Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT introduced by the commit 535d76a12150 ("armv8: layerscape: Add TFABOOT support"). This config CONFIG_TFABOOT is activated for the trusted boot chain, when U-Boot is loaded by TF-A. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: the property st, phy-cal becomes optionalPatrick Delaunay4-16/+51
This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: reduce delay after BIST reset for tuningPatrick Delaunay1-1/+1
Reduce the delay after BIST delay, from 1ms to 10us which is enough accoriding datasheet. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1_ddr: fix self refresh disable during DQS trainingPatrick Delaunay2-1/+5
DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not to enter in self refresh mode during the execution of this phase. Depending on settings, it can be set after the DQS training. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: update BIST config for tuningPatrick Delaunay1-9/+142
Update the BIST config to compute the real use mask for the real bank, row and col of the used DDR. The values are get from addrmap register value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: tuning: deactivate derating during BIST testPatrick Delaunay1-0/+15
The derating (timing parameter derating using MR4 read value) can't be activated during BIST test, as the MR4 read answer will be not understood by BIST (BISTGSR.BDONE bit stay at 0, BISTWCSR.DXWCNT = 0x206 instead of BISTWCR.BWCNT = 0x200). This patch only impacts the tuning on LPDDR2/LPDDR3, if derateen.derate_enable = 1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: tuning: add timeout for polling BISTGSR.BDDONEPatrick Delaunay1-20/+25
Avoid to block the tuning procedure on BIST error (not finished BIST procedure) by adding a 1000us timeout on the polling of BISTGSR.BDDONE executed to detect the end of BIST. The normal duration of the BIST test is around 5us. This patch also cleanup comments. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: don't display the prompt two timesPatrick Delaunay1-3/+1
Remove one "DDR>" display on command - next - step - go Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: display result for software read DQS gatingPatrick Delaunay1-4/+6
Display result information for software read DQS gating, the tuning 0 which be used by CubeMX DDR tuning tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ram: stm32mp1: increase vdd2_ddr: buck2 for 32bits LPDDRPatrick Delaunay1-5/+25
Need to increase the LPDDR2/LPDDR3 the voltage vdd2_ddr: buck2 form 1.2V to 1.25V for 32bits configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-02-13ram: rockchip: Fix Kconfig dependency for RAM_ROCKCHIP_DEBUGMichal Simek1-0/+1
There is no reason to show RAM_ROCKCHIP_DEBUG entry in other .config files as I see it for Xilinx ZynqMP. \# CONFIG_U_QE is not set \# CONFIG_RAM is not set CONFIG_RAM_ROCKCHIP_DEBUG=y Add missing dependency on RAM_ROCKCHIP driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-02-05dm: core: Drop the inclusion of linux/compat.h in dm.hSimon Glass1-0/+1
Most files don't need this header and it pulls in quite of lots of stuff, malloc() in particular. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Create a new header file for 'compat' featuresSimon Glass3-0/+3
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05dm: core: Require users of devres to include the headerSimon Glass1-0/+1
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-01-30ram: rk3328: only do data traning for cs0Kever Yang1-7/+3
No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
2020-01-30arm: rockchip: Add common cru.hJagan Teki2-10/+10
Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-01-30ram: rk3399: don't assume phy_io_config() uses real regsThomas Hebb1-4/+2
In the RK3399 DRAM driver, the function set_ds_odt() supports operating in two different modes, selected by the ctl_phy_reg argument: when true, the function reads and writes directly from the DRAM registers, accessed through "chan->pctl->denali_*"; when false, the function reads and writes from an array, accessed through "params->pctl_regs.denali_*", which is written to DRAM registers at a later time. However, phy_config_io(), which is called by set_ds_odt() to do a subset of its register operations, operates directly on DRAM registers at all times. This means that it reads incorrect values (and writes new values prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by passing in the address of the registers to work with. This prevents an "Invalid DRV value" error in the SPL debug log and (presumably) results in a more correct end state. See the following logs from a RK3399 NanoPi M4 board (4GB LPDDR3): Before: sdram_init() Starting SDRAM initialization... phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 0 phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... After: sdram_init() Starting SDRAM initialization... sdram_init() sdram_init: data trained for rank 2, ch 0 sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-01-17common: Move hang() to the same header as panic()Simon Glass4-0/+4
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17common: Move RAM-sizing functions to init.hSimon Glass4-0/+4
These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-14ram: add SDRAM driver for i.MXRT SoCsGiulio Benetti3-0/+449
Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2019-11-17rockchip: rk3308: Add sdram driverAndy Yan2-0/+56
A dm based dram driver for rk3308 u-boot to get capacity. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Fix dram setting to make dram more stableYouMin Chen1-21/+20
There are some code different with rockchip vendor code which may lead to different bugs, including: 1) Fix setting error about LPDDR3 dram size ODT. 2) Set phy io speed to 0x2. 3) Fix setting error about phy_pad_fdbk_drive. 4) Fix setting error about PI_WDQLVL_VREF_EN Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: update calculate_strideKever Yang1-39/+119
Update the calculation of the stride to support all the DRAM case. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Sync the io setting from Rockchip vendor codeKever Yang1-30/+14
The io setting are updated after some bugfix in different rk3399 boards, sync the code from vendor. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: update lpddr4 timing for rk3399Kever Yang2-9/+9
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip vendor code; Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: add support detect capacityYouMin Chen1-21/+215
Add capacity detect for rk3399 so that the driver able to detect the capacity automatically. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: update the function of sdram_initYouMin Chen1-123/+296
Clean up the sdram_init to keep sync with rockchip source code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: fix error about get_ddrc0_con reg addrYouMin Chen1-1/+1
Correct the register to its correct name. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: Clean up codeYouMin Chen1-83/+93
Clean up rk3399 dram driver source code for more readable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3399: migrate to use common codeYouMin Chen5-115/+118
For there are some structures and functions are common for all rockchip SoCs, migrate to use the common code so that we can clean up reduandent codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rk3328: use common sdram driverYouMin Chen2-606/+159
RK3328 has a similar controller and phy with PX30, so we can use the common driver for it and remove the duplicate codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: px30: add sdram driverYouMin Chen8-1/+1168
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add phy driver code for PX30Kever Yang1-0/+205
This sdram_phy_px30.c is based on PX30 SoC, the functions are common for phy, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add controller code for PX30Kever Yang1-0/+205
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common for controller, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: Default enable DRAM debug infoKever Yang1-0/+1
The debug info for dram is main about the capacity related info which is very important the board init, so set this default enable. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: move sdram_debug function into sdram_commonKever Yang3-148/+144
The functions for dram info print are part of common code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: add common code for sdram driverKever Yang3-0/+292
There are some function like os_reg setting, capacity detect functions, can be used as common code for different Rockchip SoCs, add a sdram_common.c for all these functions. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17ram: rockchip: rename sdram_common.c/h to sdram.cKever Yang8-8/+8
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c; so that we can use the file name sdram_common.c in dram driver for better understand the code; clean the related file who has use the header file at the same time. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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